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dual, 16 - bit, 1600 msps, txdac+ digital - to - analog converter data sheet ad9142 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is ass umed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or p atent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 analog devices, i nc. all rights reserved. technical support www.analog.com features very small inherent latency variation: < 2 dac clock cycles proprietary low spurious and distortion design 6 - carrier gsm aclr = 79 db c at 20 0 mhz if sfdr > 85 dbc (bandwidth = 300 mhz) at zif flexible 16 - bit lvds interface support s word and byte lo ad multiple chip synchronization fixed latency and d ata generator latency compensation selectable 2 , 4 , 8 interpolation filter low power architecture f s / 4 power saving coarse mixer input signal power detection emergency stop for downstream analog circui try protection fifo error detection on - chip numeric control oscillator allows carrier placement anywhere in the dac nyquist bandwidth transmit enable function for extra power saving high performance, low noise pll clock multiplier digital gain and p hase ad justment for sideband suppression digital inverse sinc filter support s single dac mode low power: 2.0 w at 1. 6 gsps, 1.7 w at 1.25 g sps, full operating conditions 72 - lead lfcsp applications wireless communications: 3g/4g and mc - gsm base stations, wideband repeaters, s oftware d efined r adios wideband communications: point - to - p oint , lmds/mmds transmit diversity /mimo instrumentation automated test equipment general description the ad9142 is a dual, 16 - bit, high dyna mic range digital - to - analog converter (dac) that provides a sample rate of 1 60 0 msps, permitting a multicarrier generation up to the nyquist frequency. the ad9142 txda c+ ? in cludes features optimized for direct c onversion transmit applications, including complex digital mod - ulatio n, input signal power detection, and gain, phase , and offset compensation. the dac outputs are optimized to interface seamlessly with analog quadrature modulators, such as the adl537x f - m od series and the adrf670x series from analog devices, inc. a 3 - wire serial port interface provides for the pro - gram ming/readback of many internal parameters. full - scale output current can be programmed over a range of 9 ma to 33 ma. the ad9142 is available in a 72 - lead lfcsp. product highlights 1. advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies . 2. very small inher ent latency variation simplifies both software and hardware design in t he system. it allows easy multi chip synchronization for most applications. 3. new low power architecture improves power efficiency (mw/mhz/channel) by 30% . 4. input signal power and fifo erro r detection simplify designs for downstream analog circuitry protection. 5. programmable transmit enable function allows easy design balance between power consumption and wakeup time.
ad9142 data sheet rev. 0 | page 2 of 64 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 product highligh ts ........................................................................... 1 revision history ............................................................................... 3 functional block diagram .............................................................. 4 specifications ..................................................................................... 5 dc specifications ......................................................................... 5 digital specifications ................................................................... 6 dac latency specifica tions ........................................................ 7 latency variation specifications ................................................ 7 ac specifications .......................................................................... 7 oper ating speed specifications .................................................. 8 absolute maximum ratings ....................................................... 9 thermal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 12 terminology .................................................................................... 17 serial port operation ..................................................................... 18 data format ................................................................................ 18 serial port pin descriptions ...................................................... 18 serial port options ..................................................................... 18 data interface .................................................................................. 20 lvds input data ports .............................................................. 20 word interface mode ................................................................. 20 byte interface mode ................................................................... 20 data interface configuration options .................................... 20 interface delay line ................................................................... 22 fifo operation .............................................................................. 23 resetting the fifo ..................................................................... 24 serial port initiated fifo reset ............................................... 24 f rame initiated fifo reset ....................................................... 24 digital datapath .............................................................................. 26 interpolation filters ................................................................... 26 digital modulation ..................................................................... 28 datapath configuration ............................................................ 29 digital quadrature gain and phase adjustment ................... 29 dc offset adjustment ............................................................... 29 inverse sinc filter ....................................................................... 30 input signal power detection and protection ........................ 30 transmit enable function ......................................................... 31 digital function configuration ............................................... 31 multidevice synchron ization and fixed latency ....................... 32 very small inherent latency variation ................................... 32 further reducing the latency variation ................................. 32 synchronization implementation ............................................ 33 synchronization procedures ..................................................... 33 interrupt request ope ration ........................................................ 34 interrupt working mechanism ................................................ 34 interrupt service routine .......................................................... 34 temperature sensor ....................................................................... 35 dac input clock configurations ................................................ 36 driving the dacclk and refclk inputs ........................... 36 direct clocking .......................................................................... 36 clock multiplication .................................................................. 36 pll settings ................................................................................ 37 configuring the vco tuning band ........................................ 37 automatic vco band select .................................................... 37 manual vco band select ......................................................... 37 analog outputs ............................................................................... 38 transmit dac operation .......................................................... 38 interfacing to modulators ......................................................... 39 reducing lo leakage and unwanted sidebands .................. 40 example start - up routine ............................................................ 41 dev ice configuration register map and description ............... 42 spi configure register .............................................................. 44 power - down control register ................................................. 44 interrupt enable0 register ........................................................ 44 interrupt enable1 register ........................................................ 44 interrupt flag0 register ............................................................. 45 interrupt flag1 register ............................................................. 45 interrupt select0 register .......................................................... 45 interrupt s elect1 register .......................................................... 46 dac clock receiver control register .................................... 46 ref clock receiver control register ....................................... 46 pll control register ................................................................. 47 pll control register ................................................................. 47 pll control register ................................................................. 47 pll status register ..................................................................... 48
data sheet ad9142 rev. 0 | page 3 of 64 pll status register ..................................................................... 48 idac fs adjust lsb register .................................................... 48 idac fs adjust msb register .................................................. 48 qdac fs adjust lsb register .................................................. 48 qdac fs adjust msb regi ster ................................................ 49 die temperature sensor control register ............................... 49 die temperature lsb register .................................................. 49 die temperature msb register ................................................. 49 chip id register .......................................................................... 49 interrupt configuation register ............................................... 50 sync ctrl register .................................................................... 50 frame reset ctrl register ....................................................... 50 fifo level configuration register .......................................... 51 fifo level readback register .................................................. 51 fifo ctrl register ................................................................... 51 data format select register ....................................................... 52 datapath control register ......................................................... 52 interpolation control register .................................................. 52 over threshold ctrl0 register .............................................. 53 over threshold ctrl1 register .............................................. 53 over threshold ctrl2 register .............................................. 53 input power readback lsb register ........................................ 53 input power readback msb register ....................................... 53 nco control regi ster ................................................................ 54 nco_freq_tuning_word0 register ............................. 54 nco_freq_tuning_word1 register ............................. 54 nco_freq_tuning_word2 register ............................. 54 nco_freq_tuning_word3 register ............................. 54 nco_phase_offset0 register ............................................ 54 nco_phase_offset1 register ............................................ 55 iq_phase_adj0 register ........................................................ 55 iq_phase_adj1 register ........................................................ 55 idac_dc_offset0 register .................................................. 55 idac_dc_offset1 register .................................................. 55 qdac_dc_offset0 reg ister ................................................ 55 qdac_dc_offset1 register ................................................ 56 idac_gain_adj register ....................................................... 56 qdac _gain_adj register ..................................................... 56 gain step control0 register ...................................................... 56 gain step control1 register ...................................................... 56 tx enable control register ...................................................... 57 dac output control register .................................................. 57 data receiver test control register ......................................... 57 data receiver test control register ......................................... 57 device configuration0 register ................................................ 58 ve rsion register .......................................................................... 58 device configuration1 register ................................................ 58 device configuration2 register ................................................ 58 dac latency and system skews ................................................... 59 dac latency variations ............................................................. 59 fifo latency variation .............................................................. 59 clock generation latency variation ........................................ 60 correcting system skews ........................................................... 60 packaging and ordering information .......................................... 61 outline dimensions .................................................................... 61 ordering guide ........................................................................... 61 revision history 1 1 / 12 rev ision 0: initial version
ad9142 data sheet rev. 0 | page 4 of 64 functional block dia gram figure 1. ref and bias fsadj refio power-on reset multichip synchronization serial input/output port programming registers sdio sclk cs reset txen irq1 irq2 dacclkp dacclkn refp/syncp refn/syncn clock multiplier clk rcvr ref rcvr dac_clk lvds data receiver input power detection fifo 8-sample d15p/d15n d0p/d0n framep/ framen dcip/dcin interface ctrl fifo ctrl interp mode ctrl1 hb1 2 interp mode ctrl2 hb2 2 interp mode ctrl3 hb3 2 dac_clk inv sinc gain and phse control dc offset control over-threshold protection complex modulation f dac /4 mod nco dac 1 16-bit iout1p iout1n 16 dac 2 16-bit iout2p iout2n 16 10 gain 1 10 gain 2 internal clock timing and control logic dac clk sync ad9142 10930-001
data sheet ad9142 rev. 0 | page 5 of 64 specifications dc specifications t min to t max , av dd 3 3 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i outfs = 20 ma, maximum sample rate, unless otherwise noted. table 1 . parameter test conditions/comments min typ max unit resolution 16 bits accuracy differential nonlinearity (dnl) 2.1 lsb integral nonlinearity (inl) 3.7 lsb main dac outputs offset error ? 0.001 0 + 0.001 % fsr gain error w ith internal reference ? 3.2 2 4.7 % fsr full - scale output current based on a 10 k external resistor between fsadj and avss 19.06 19.8 + 20.6 ma output compliance range ? 1.0 + 1.0 v output resistance 10 m gain da c monotonicity guaranteed settling time to within 0.5 lsb 20 ns main dac temperature drift offset 0.04 ppm/ c gain 100 ppm/ c reference voltage 30 ppm/ c reference internal reference voltage 1.17 1.19 v output resistance 5 k analog supply voltages avdd 33 3.13 3.3 3.47 v cvdd 18 1.71 1.8 1.89 v digital supply voltages dvdd 18 1.71 1.8 1.89 v power consumption 2 mode f dac = 491.52 msps nco off 700 mw nco on 870 mw 4 mode f dac = 737.28 msps nco off 836 mw nco on 1085 mw 4 mode f dac = 983.04 msps nco off 1030 mw nco on 1365 mw 8 mode f dac = 1600 msps nco off 1315 mw nco on 1815 mw phase - lock loop 70 mw inverse s inc f dac = 1474.56 msps 113 mw red uced power mode ( power down ) 96.6 mw avdd 33 1.5 ma cvdd 18 42.3 ma dvdd 18 8.6 ma operating range ? 40 + 25 + 85 c
ad9142 data sheet rev. 0 | page 6 of 64 digital specificatio ns t min to t max , av dd 3 3 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i outfs = 20 ma, maximum sampl e rate, unless otherwise noted. table 2 . parameter symbol test conditions /comments min typ max un it cmos input logic level input logic high d vdd 18 = 1.8 v 1.2 v logic low d vdd 18 = 1.8 v 0.6 v cmos output logic level output logic high d vdd 18 = 1.8 v 1.4 v logic low d vdd 18 = 1.8 v 0.4 v lvds receiver inputs input voltage range v ia or v ib 825 1675 mv input differential threshold v idth data and frame inputs ? 100 + 100 mv dci input ? 225 + 225 mv input differential hysteresis v idthh to v idthl 20 mv receiver differential input impedance r in 120 dac update rate 1600 msps dac adjusted update rate 2 i nterpolation 250 msps dac clock input (da cclkp, dacclkn) differential peak -to - peak voltage 100 500 2000 mv common - mode voltage self biased input, ac - couple d 1.25 v refclk/syncclk input ( refp/syncp , refn/syncn ) differential peak -to - peak voltage 100 500 2000 mv common - mode voltage 1.25 v input clock frequency 1 ghz f vco 2.1 g hz 450 mhz serial p ort interface maximum clock rate sclk 40 mhz minimum pulse width high t pwh 12.5 ns low t pw l 12.5 ns setup time t ds sdi o to sclk 1. 5 ns hold time t dh sdi o to sclk 0. 68 ns setup tim e t dcsb cs to sclk 2.38 1.4 ns
data sheet ad9142 rev. 0 | page 7 of 64 dac latency specifications t min to t max , av dd 3 3 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i outfs = 20 ma, fifo l evel is set to 4 (half of the fifo depth), unless otherwise noted. table 3 . parameter test conditions/comments min typ max unit word interface mode fine/coarse modulation, inverse sinc, gain/phase compensation off 2 interpolation 134 dacclk c ycles 4 interpolation 244 dacclk c ycles 8 interpolation 481 dacclk c ycles byte interface mode fine/coarse modulation, inverse sinc, gain/phase compensation off 2 interpolation 145 dacclk c ycles 4 interpolation 271 dacclk c ycles 8 interpolation 506 dacclk c ycles individual function blocks modulation fine 17 dacclk c ycles coarse 10 dacclk c ycles inverse sinc 20 dacclk c ycles phase compensation 12 dacclk c ycles gain compensation 16 dacclk c ycles latency v ariation specifications 1 table 4 . parameter min typ max unit dac latency variation sync o ff 2 dacclk cycles sync o n 1 dacclk cycles 1 dac latency is defined as the elapsed time from a data sample clocked at the inp ut to the ad9142 until the analog output begins to change. ac specifications t min to t max , av dd 3 3 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i outfs = 20 ma, maximum sample rate, unless otherwise noted . table 5 . parameter test conditions/comments min typ max unit spurious - free dynamic range (sfdr) ? 14 dbfs single tone f dac = 737.28 msps f out = 200 mhz bw = 125 mhz 85 dbc bw = 270 mhz 80 dbc f dac = 983.04 msps f out = 200 mhz bw = 360mhz 85 dbc f dac = 1228.8 msps f out = 280 mhz bw = 200mhz 85 dbc bw = 500mhz 75 d bc f dac = 1474.56 msps bw = 737mhz f out = 10 mhz 85 dbc bw = 400mhz f out = 280 mhz 80 dbc two - tone intermodulation distortion (imd) ? 6 dbfs each tone f dac = 737.28 msps f out = 200 mhz 80 dbc f dac = 983.04 msps f out = 200 mhz 82 dbc f dac = 1228.8 msps f out = 280 mhz 80 dbc f dac = 1474.56 msps f out = 10 mhz 85 dbc f out = 280 mhz 79 dbc
ad9142 data sheet rev. 0 | page 8 of 64 parameter test conditions/comments min typ max unit noise spectral density (nsd ) e ight - tone, 500 k h z tone spacing f dac = 737.28 msps f out = 200 mhz ? 160 dbm/hz f dac = 983.04 msps f out = 200 mhz ? 161.5 dbm/hz f dac = 1228.8 msps f out = 280 mhz ? 164.5 dbm/hz f dac = 1474.56 msps f out = 10 mhz ? 166 dbm/hz f out = 280 mhz ? 162.5 dbm/hz w - cdma adjacent channel leakage ratio (aclr) single c arrier f dac = 983.04 msps f out = 200 mh z 81 dbc f dac = 1228.8 msps f out = 20 mhz 83 dbc f out = 280 mhz 80 dbc f dac = 1474.56 msps f out = 20 mhz 81 dbc f out = 280 mhz 80 dbc w - cdma second ( aclr ) single carrier f dac = 983.04 msps f out = 200 mhz 85 dbc f dac = 1228.8 msps f out = 20 mhz 8 6 dbc f out = 280 mhz 8 6 dbc f dac = 1474.56 msps f out = 20 mhz 86 dbc f out = 280 mhz 85 dbc operating speed specifications t able 6 . interpolation factor dvdd 18 , cvdd18 = 1.8 v 5% dvdd18, cvdd18 = 1.8 v 2% or 1.9 v 5% f interface (mbps) max f dac (mbps) max f interface (mbps) max f dac (mbps) max 2 250 500 250 500 4 250 1000 250 1000 8 187.5 1500 200 1600
data sheet ad9142 rev. 0 | page 9 of 64 absolute maximum rat ings table 7 . parameter rating avdd 33 to avss, epad, cvss, dvss ? 0.3 v to + 3.6 v dvdd18, cvdd18 to avss, epad, cvss, dvss ? 0.3 v to + 2.1 v avss to epad, cvss, dvss ? 0.3 v to + 0.3 v epad to avss, cvss, dvss ? 0.3 v to + 0.3 v cvss to avss, epad, dvss ? 0.3 v to + 0.3 v dvss to avss, epad, cvss ? 0.3 v to + 0.3 v fsadj, refio, iout1p/iout1n, iout2p/i out2n to avss ? 0.3 v to avdd 33 + 0.3 v d[15:0]p/d[15:0]n, framep/framen, dcip/dcin to epad, dvss ? 0.3 v to dvdd 18 + 0.3 v dacclkp/dacclkn, refp/syncp/refn/syncn to cvss ? 0.3 v to cvdd 18 + 0.3 v reset , irq 1 , irq 2 , cs , sclk, sdio to epad, dvss ? 0.3 v to dvdd18 + 0.3 v junction temperature 125 c storage temperature range ? 65 c to + 150 c thermal resistance the exposed pad (epad) must be soldered to th e ground plane (avss) for the 72 - lead lfcsp . the epad provides an electrical, thermal, and mechanical connection to the board. typical ja , jb , and jc values are specified for a 4 - layer board in still air. airflow increases heat dissipation, effectively reducing ja and jb . table 8 . thermal resistance package ja jb jc unit conditions 72 - lead lfcsp 20.7 10.9 1.1 c/w epad soldered to ground plane esd caution s t r e s s es a b o ve t h o s e l i s t e d u n d e r a b s o l u t e m a x i m um r a t i n gs m a y c a u s e p e r m a n e n t dam a g e t o t h e d e v i c e . this is a s t r e s s r a t i n g o n l y ; fu n c t i o n a l o p e r a t i o n o f t h e d ev i c e a t t h e s e o r a n y o t h e r co n d i t i o ns a b o ve t h o s e indi c a t e d i n t h e o p e r a t i o na l s e c t i o n o f t h is s p e c i fi c a t ion is n o t i m p l i e d . e x p o su r e t o a b s o l u te ma x i m u m r a t in g c o n d i t i o n s fo r e x t e n d e d p e r i o d s m a y a ff e c t d e vi c e r e l i a b i l i t y .
ad9142 data sheet rev. 0 | page 10 of 64 pin configuration an d function descripti ons figure 2 . pin configuration table 9 . pin function descriptions pin no. mnemonic description 1 c vdd 18 1.8 v pll supply. cvdd18 s upplies the clock receivers, clock multiplier, and clock distribution. 2 refp/syncp pll re ference clock input, positive. 3 refn/syncn pll reference clock input, negative. 4 c vdd 18 1.8 v pll supply. cvdd18 supplies the clock receivers, clock multiplier, and clock distribution. 5 reset reset, active low. cmos l evels with r esp ect to dvdd18. recommended reset pulse length is 1 s. 6 txen ac tive high transmit path enable. cmos l evels with r espect to dvdd 18 . a low level on this pin triggers three selectable actions in the dac. see reg ister 0x43 in table 7 7 for details . 7 dvdd 18 1.8 v digital supply. pin 7 s upplies power to the digital core, digital data ports, serial port input/output p ins , reset , irq 1 , and irq 2 . 8 framep frame input, positive. 9 f ramen frame input, negative. 10 d 15p data bit 15 (msb), positive. 11 d 15n data bit 15 (msb), negative. 12 dvdd 18 1.8 v digital supply. pin 12 s u pplies the power to the digital core and digital data ports. 13 d 14p data bit 14 , positive. 14 d 14n data bi t 14 , negative. 15 d 13p data bit 13 , positive. 16 d 13n data bit 13 , negative. 17 d 12p data bit 12 , positive. 18 d 12n data bit 12 , negative. 19 dvdd 18 1.8 v digital supply. pin 19 s u pplies power to the digital core, digital data ports , serial port inpu t/output pins , reset , irq 1 , and irq 2 . 20 d 11p data bit 11 , positive. 2 1 d 11n data bit 11 , negative. 2 2 d 10p data bit 10 , positive. 2 3 d 10 n data bit 10 , negative. 2 4 d 9 p data bit 9 , positive. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cvdd18 refp/syncp refn/syncn cvdd18 reset txen dvdd18 framep framen d15p d15n dvdd18 d14p d14n d13p d13n 17 d12p 18 d12n 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 dvdd18 d11p d11n d10p d10n d9p d9n d8p d8n dcip dcin d7p d7n d6p d6n d5p 35 d5n 36 dvdd18 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 cs sclk sdio irq1 irq2 dvdd18 dvdd18 d0n d0p d1n d1p dvdd18 d2n d2p d3n d3p d4n d4p 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 cvdd18 cvdd18 refio fsadj avdd33 iout1p iout1n avdd33 cvdd18 cvdd18 dacclkn dacclkp cvdd18 cvdd18 avdd33 iout2n iout2p avdd33 ad9142 top view (not to scale) notes 1. exposed pad (epad) must be soldered to the ground plane (avss). the epad provides an electrical, thermal, and mechanical connection to the board. 2. epad is the ground connection for cvss and dvss. 10930-002
data sheet ad9142 rev. 0 | page 11 of 64 pin no. mnemonic description 2 5 d9 n data bit 9 , negative. 2 6 d 8 p data bit 8 , positive. 2 7 d 8 n data bit 8 , negative. 2 8 dcip data clock input, positive. 2 9 dcin data clock input, negative. 3 0 d 7 p data bit 7 , positive. 3 1 d 7 n data bit 7 , negative. 3 2 d 6 p data bit 6 , positive. 3 3 d 6 n data bit 6 , negative. 3 4 d 5 p data bit 5 , positive. 3 5 d 5 n data bit 5 , negative. 36 dvdd 18 1.8 v digital supply. pin 36 s u pplies power to the digital core, digital data ports , serial port input/output p ins , reset , irq 1 , and irq 2 . 3 7 d 4 p data bit 4 , positive. 3 8 d 4 n data bit 4 , negative. 39 d 3 p data bit 3 , positive. 40 d 3 n data bit 3 , negative. 41 d 2 p data bit 2 , positive. 42 d 2 n data bit 2 , negative. 43 dvdd 18 1.8 v digital supply. pin 43 s u ppl ies power to the digital core, digital data ports , serial port input/output p ins , reset , irq 1 , and irq 2 . 4 4 d 1 p data bit 1 , positive. 4 5 d 1 n data bit 1 , negative. 4 6 d 0 p data bit 0 (lsb) , positive. 4 7 d 0 n data bit 0 (lsb) , negative. 4 8 dvdd 18 1.8 v digital supply. pin 48 s u pplies power to the digital core, digital data ports , serial port input/output pins , reset , irq 1 , and irq 2 . 49 dvdd 18 1.8 v digital supply. pin 49 s upplies power to the digital core, digital data ports, serial port input/output pins , reset , irq 1 , and irq2 . 50 irq 2 second interrupt request. open - drain, ac tive low output. connect an external pull - up to dvdd18 through a 10 k resistor. 51 irq 1 first interrupt request. open - drain, active low output. connect an external pull - up to dvdd18 through a 10 k resistor. 5 2 sdio serial port data in put/output. cmos l evels with r espect to dvdd18. 5 3 sclk serial port clock input . cmos l evels w ith r espect to dvdd18 . 5 4 cs serial port chip select . active l ow (cmos levels w ith respect to dvdd18 ). 55 avdd 33 3.3 v analog supply. 5 6 iou t 2 p qdac positive current output. 5 7 iout 2 n qdac negative current output. 5 8 avdd 33 3.3 v analog supply. 59 cvdd 18 1.8 v clock s upply. supplies clock receivers and clock distribution. 60 cvdd 18 1.8 v clock s upply. supplies clock receivers and clock di stribution. 6 1 dacclkn dac clock input, negative. 6 2 dacclkp dac clock input, positive. 63 cvdd 18 1.8 v clock s upply. supplies clock receivers and clock distribution. 64 cvdd 18 1.8 v clock s upply. supplies clock receivers and clock distribution. 6 5 av dd33 3.3 v analog supply. 6 6 iout 1 n i dac negative current output. 6 7 iout 1 p i dac positive current output. 6 8 avdd 33 3.3 v analog supply. 6 9 fsadj full - scale current output adjust. place a 10 k resistor from this pin to avss . 70 refio voltage reference. nominally 1.2 v output. decouple refio to avss . 71 cvdd 18 1.8 v clock s upply. pin 71 s upplies the clock receivers, clock multiplier, and clock di stribution. 72 cvdd 18 1.8 v clock s upply. pin 72 s upplies the clock receivers, clock multiplier, and clock distribution. epad exposed pad. the exposed pad (epad) must be soldered to the ground plane (avss). the epad provides an electrical, thermal, and mechanical connection to the board.
ad9142 data sheet rev. 0 | page 12 of 64 typical performance characteristics figure 3 . single- tone (0 dbfs) sfdr vs. f out in the first nyquist zone over f dac figure 4 . single- tone second harmonic vs. f out in the first nyquist zone over digital bac k off , f dac = 1474.56 mhz figure 5 . single- tone third harmonic vs. f out in the first nyquist zone over digital b ack off , f dac = 1474.56 mhz figure 6 . single- tone sfd r (e xcluding 2 nd h armonic) vs. f o ut in 80 mhz and 300 mhz b andwidths , f dac = 737.28 mhz figure 7 . single- t one sfdr (e xcluding 2 nd h armonic) vs. f out i n 80 mhz and 300 mhz bw, f dac = 983.04 mhz figure 8 . single- tone sf dr (e xcluding 2 nd h armonic) vs. f o ut in 80 mhz and 300 mhz b andwidths , f dac = 1228.8 mhz 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 200 300 400 500 600 700 800 sfdr (dbc) f out (mhz) f dac = 737.28mhz f dac = 983.04mhz f dac = 1228.8mhz f dac = 1474.56mhz 10930-003 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 200 300 400 500 600 700 800 second harmonic (dbc) f out (mhz) 0dbfs ?6dbfs ?12dbfs ?16dbfs 10930-005 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 200 300 400 500 600 700 800 third harmonic (dbc) f out (mhz) 0dbfs ?6dbfs ?12dbfs ?16dbfs 10930-007 ?60 < ?85 ?85 ?80 ?75 ?70 ?65 0 20 40 60 80 100 140 180 120 160 200 in-band sfdr (dbc) f out (mhz) bw = 80mhz, ?6dbfs bw = 80mhz, ?12dbfs bw = 300mhz, ?6dbfs bw = 300mhz, ?12dbfs 10930-004 C85 means C85 ?60 < ?85 ?85 ?80 ?75 ?70 ?65 0 300 250 200 150 100 50 in-band sfdr (dbc) f out (mhz) bw = 80mhz, ?6dbfs bw = 80mhz, ?12dbfs bw = 300mhz, ?6dbfs bw = 300mhz, ?12dbfs 10930-006 C85 means C85 ?60 < ?85 ?85 ?80 ?75 ?70 ?65 0 350 300 250 200 150 100 50 in-band sfdr (dbc) f out (mhz) bw = 80mhz, ?6dbfs bw = 80mhz, ?12dbfs bw = 300mhz, ?6dbfs bw = 300mhz, ?12dbfs 10930-008 C85 means C85
data sheet ad9142 rev. 0 | page 13 of 64 figure 9. single - to ne sfdr (e xcluding 2 nd h armonic) v s. f out in 80 mhz and 300 mhz b andwidths , f dac = 1474.56 mhz figure 10 . two - tone third imd vs. f out over f dac figure 11 . two - tone third i md vs. f out over digital back off , f dac = 1474.56 mhz figure 12 . two - tone third imd vs. f out over tone spacing , f dac = 1474.56 mhz figure 13 . single - tone (0 dbfs) nsd vs. f out over f dac figure 14 . single - tone nsd vs. f out over digital b ack off , f dac = 1474.56 mhz ?60 < ?85 ?85 ?80 ?75 ?70 ?65 0 350 300 250 200 150 100 50 in-band sfdr (dbc) f out (mhz) bw = 80mhz, ?6dbfs bw = 80mhz, ?12dbfs bw = 300mhz, ?6dbfs bw = 300mhz, ?12dbfs 10930-009 C85 means C85 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 200 300 400 500 600 700 800 imd (dbc) f out (mhz) f dac = 737.28mhz f dac = 983.04mhz f dac = 1228.8mhz f dac = 1474.56mhz 10930-0 1 1 0 ?120 ?100 ?80 ?60 ?40 ?20 0 800 600 700 500 400 300 200 100 imd (dbc) f out (mhz) 0dbfs ?6dbfs ?9dbfs 10930-013 0 ?120 ?100 ?80 ?60 ?40 ?20 0 800 600 700 500 400 300 200 100 imd (dbc) f out (mhz) 0.6mhz tone spacing 16mhz tone spacing 35mhz tone spacing 10930-010 ?152 ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 0 100 200 300 400 500 600 700 800 nsd (dbm/hz) f out (mhz) f dac = 737.28mhz f dac = 983.04mhz f dac = 1228.8mhz f dac = 1474.56mhz 10930-012 ?152 ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 0 100 200 300 400 500 600 700 800 nsd (dbm/hz) f out (mhz) 0dbfs ?6dbfs ?12dbfs ?16dbfs 10930-014
ad9142 data sheet rev. 0 | page 14 of 64 figure 15 . 1c wcdma nsd vs. f out , over f dac figure 16 . single - tone nsd vs. f out , f dac = 1474.28 mhz, pll o n and o ff figure 17 . 1c wcdma 1 st a djacent aclr vs. f out , pll on and off figure 18 . 1c wcdma 2 nd a djacent aclr vs. f out , pll on and off figure 19 . two - tone third imd p erformance, if = 280 mhz, f dac = 1474.28 mhz figure 20 . 1c wcdma aclr p erformance, if = 280 mhz, f dac = 1474.28 mhz ?150 ?152 ?170 ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 0 100 200 300 400 500 600 700 800 nsd (dbm/hz) f out (mhz) 10930-200 737.2mhz 983.04mhz 1228.8mhz 1474.56mhz ?150 ?152 ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 0 100 200 300 400 500 600 700 800 nsd (dbm/hz) f out (mhz) pll off pll on 10930-015 ?60 ?85 ?80 ?75 ?70 ?65 0 100 200 300 400 500 600 700 800 aclr (dbc) f out (mhz) 10930-100 f dac = 1474.56mhz, pll off, 0dbfs f dac = 1474.56mhz, pll on, 0dbfs f dac = 1228.8mhz, pll off, 0dbfs f dac = 1228.8mhz, pll on, 0dbfs ?60 ?90 ?85 ?80 ?75 ?70 ?65 0 100 200 300 400 500 600 700 800 aclr (dbc) f out (mhz) 10930-101 f dac = 1474.56mhz, pll off, 0dbfs f dac = 1474.56mhz, pll on, 0dbfs f dac = 1228.8mhz, pll off, 0dbfs f dac = 1228.8mhz, pll on, 0dbfs 10930-016 10930-017
data sheet ad9142 rev. 0 | page 15 of 64 figure 21 . single - tone f da c = 1474.56 mhz, f out = 280 mhz, ? 14 dbfs figure 22 . 4 c wcdma aclr p erformance, if = 280 mhz, f dac = 1474.28 mhz figure 23 . sin gle - tone sfdr f dac = 1474.56 mhz, 4 interpolation, f out = 10 mhz, ? 14 dbfs figure 24 . total power consumption vs. f dac over interpolation figure 25 . dvdd18 current vs . f dac over interpolation figure 26 . dvdd18 current vs . f dac ove r digital functions 10930-018 10930-019 10930-020 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 0 1800 1600 1400 1200 1000 800 600 400 200 power (w) f dac (mhz) 10930-021 2 interpolation 4 interpolation 8 interpolation 450 0 50 100 150 200 250 300 350 400 0 1800 1600 1400 1200 1000 800 600 400 200 dvdd18 (ma) f dac (mhz) 10930-024 2 interpolation 4 interpolation 8 interpolation 0.30 0.25 0.20 0.15 0.10 0.05 0 0 200 400 600 800 1000 1200 1400 1600 dvdd18 (ma) f dac (mhz) nco inv sinc dig gain, phase, and offset 10930-022
ad9142 data sheet rev. 0 | page 16 of 64 figure 27 . cvdd18, avdd33 current vs. f dac 250 200 150 100 50 0 0 200 400 600 800 1000 1200 1400 1600 supply current (ma) f dac (mhz) cvdd18 pll off avdd33 cvdd18 pll on 10930-023
data sheet ad9142 rev. 0 | page 17 of 64 terminology integral nonlinearity (inl) inl is the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full s cale. differential nonlinearity (dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. offset error offset error is t he deviation of the output current from the ideal of 0 ma . for iout1p, 0 ma output is expected when all inputs are set to 0 . for iout 1 n, 0 ma output is expected when all inputs are set to 1 . gain error gain error is t he difference between the actual and ideal output span. the actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0 . output compliance range the o utput c ompliance r ange is t he range of allowable voltage at the output of a current output dac. operation beyond the maxim um compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full - scale range (fsr) per degree celsius. for reference drift, the drift is reported in ppm per degree celsius. power supply rejection (psr) psr is t he maximum change in the full - scale output as the s upplies are varied from minimum to maximum specified voltages. settling time settling t ime is t he time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. spur ious free dynamic range (sfdr) sfdr is t he difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to nyquist frequency of the dac. typically, the interpoloation filters reject energy in this band . this specification, there fore, defines how well the interpolation filters work and the effect of other parasitic coupling paths on the dac output. signal -to - noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. interpolation filter if the digital inputs to the dac are sampled at a multiple rate of f data (interpolation rate), a digital filter can be constructed that has a sharp transition band near f data /2. images that typically appear around f dac (output data rate) can be greatly suppressed. adjacent channel leakage ratio (aclr) aclr is the ratio in decibels relative t o the carrier (dbc) between the measured power within a channel relative to its adjacent channel. complex image rejection in a traditional two - part upconversion, two images are created around the second if frequency. these images have the effect of wastin g transmitter power and system bandwidth. by placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second if can be rejected.
ad9142 data sheet rev. 0 | page 18 of 64 serial port operatio n the serial p ort is a flexible, synchronous serial communications port that allows easy interfacing to many industry standard micro - controllers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including both the motorola spi and intel? ssr protocols. the interface allows read/write access to all registers that configure the ad9142 . msb - first or lsb - first transfer formats are supported. the serial port interface is a 3 - wire only interfa ce. the input and output share a single pin input/output (sdio) . figure 28 . serial port interface pins there are two phases to a communication cycle with the ad9142 . phase 1 is the i nstruction cycle (the writing of an instruction byte into the device), coincident with the first 16 sclk ri sing edges. the instruction word provides the serial port controller with information regarding the data transfer cycle, phase 2 , of the communicatio n cyc le. the phase 1 instruction word defines whether the upcoming data transfer is a read or write , along with the starting reg ister address for the following d ata transfer . a logic high on the cs pin , followed by a logic low , resets th e serial port timing to the initial state of the instruction cycle. from this state, the next 16 rising sclk edges represent the instruction bits of the current i/o operation. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the device and the system controller. phase 2 of the communication cycle is a transfer of one data byte . registers change immediately upon writing to the last bit of each transfer byte, except for the frequency tuning word and nco phase offsets, which change only when the frequency tuning word (ftw) u pdate bit is set. data format the instruction byte contains the information shown in table 10 . table 10 . seria l port i nstruction word i 15 (msb) i[ 14:0 ] r/ w a[ 14:0 ] r/ w ( bit 15 of the instruction word ) determines whether a read or a write data transfer o ccurs after the instruction word write. log ic 1 indicates a read operation and logic 0 indicates a write operation. a14 to a0 ( bit 14 to bit 0 of the instruction word ) determine the register that is accessed during the data transfer portion of the com munication cycle. for multibyte transfers, a14 is the starting address ; t he de vice generates the remaining register addresses based on the spi_ lsb_first bit. serial port pin desc riptions serial clock (sclk) the serial clock pin synchronizes data to and from the device and runs the internal state machines. the maximum frequency of sc lk is 40 mhz. all data input is registered on the rising edge of sclk. all data is driven out on the falling edge of sclk. chip select ( cs ) cs is a n active low input that starts and gates a communication cycle. it allows more than one device to be used on the same serial commu nications line . the sdio pins enter a high impedance state when th e cs input is high. during the communication cycle, cs should stay low. serial data i/o (sdio) th e sdio pin is a bidirectional data line. serial port options the serial p ort can support both msb - first and lsb - first data formats. this functionality is controlled by the spi_lsb_first bit ( register 0 x 00 , bit 6 ). the default is msb first (lsb_first = 0 ). when spi_lsb_first = 0 (msb first), the instruction and data bits must be written from msb to lsb. multibyte data transfers in msb - first format start with an instruction word that includes the register address of the most significant data byte. subsequent data bytes must follow from high address to low address. in msb - first mode, the serial port internal word address generator decrements for each data byte of the multibyte communication cycle. when spi_lsb_first = 1 (lsb first), the instruction and data bit s must be written from lsb to msb. multibyte data transfers in lsb - first format start with an instruction word that includes the register address of the least significant data byte. subsequent data bytes must follow from low address to high address. in lsb - f irst mode, the serial port internal word address generator increments for each da ta byte of the multibyte communication cycle. if the msb - first mode is active, the serial port controller data address decrements from the data address written toward 0x00 f or multibyte i/o operations. if the lsb - first mode is active, the serial port controller data address increments from the data address written toward 0xff for m ultibyte i/o operations. 53 sclk 54 cs 52 sdio spi port 10930-025
data sheet ad9142 rev. 0 | page 19 of 64 figure 29 . serial register interface timin g, msb first figure 30 . serial register interface timing, lsb first figure 31 . timing diagram for serial port register write figure 32 . timing diagram for serial port register read r/w a14 a13 a3 a2 a1 a0 d7 n d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle data transfer cycle sclk sdio cs 10930-026 a0 a1 a2 a12 a13 a14 r/w d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n instruction cycle data transfer cycle sclk sdio cs 10930-027 sclk sdio cs instruction bit 14 instruction bit 15 t dcsb t ds t dh t pwh t pwl t sclk 10930-028 sclk sdio cs d at a bit n ? 1 d at a bit n t dv 10930-029
ad9142 data sheet rev. 0 | page 20 of 64 data interface lvds input data port s the ad9142 has a 16 - bit lvds bus that accepts 16 - bit i and q data either in word wide (16 - bit) or byte wide (8 - bit) formats. in the word wide interfac e mode, the data is sent over the entire 16- bit data bus. in the byte wide interface mode, the data is sent over the lower 8 - bit (d7 to d0) lvds bus. table 11 lists t he pin assignment of the bus and the spi registe r configuration for each mode . table 11. lvds data input modes interface mode pin assignment spi register configuration word d 15 to d0 register 0 x26 , b it 0 = 0 byte d7 to d 0 register 0 x26 , b it 0 = 1 word interface mode in word mo de, the digital clock input ( dci ) signal is a reference bit that generate s a double data rate (ddr) data sampling clock . t ime align t he dci signal with the data. the i dac data follow s the rising edge of the dci , and the qdac data follow s the falling edge o f the dci , as shown in figure 33. figure 33 . timing diagram for word mode byte interface mode in byte mode, the required sequence of the input data stream is i[15:8], i[7:0], q[15:8], q [7:0]. a frame sig nal is required to align the order of input data bytes properly . time align b oth t he dci signal and frame signal with the data. the rising edge of the frame indicates the start of the sequence. the frame can be either a one shot or period ical signal as long as its first rising edge is correctly captured by the device. for a one shot frame , the frame pulse needs to hold at high for at least one dci cycle. for a periodical frame , the frequency needs to be f dci /(2 n) where n is a positive integer , that is, 1, 2, 3 , figure 34 is an example of signal timing in byte mode. figure 34 . timing diagram for byte mode data interface configuration options to provide more flexibility for the data interface , some additional options are listed in table 12. table 12. data interface configuration options register 0 x 26 function data format (bit 7 ) select between b inary and two s c omplement format s. da ta pa i ring (bit 6 ) indicate i/q data pairing on data input. this allows the i and q data that is received to be paired in various ways. data bus invert (bit 5 ) swap s the bit order of the data input port. remap s the input data from d [ 15: 0 ] to d [0: 15] . i 0 q 0 i 1 q 1 word mode dci input data[15:0] 10930-030 i 0[15:8] i 0[7:0] q 0[15:8] q 0[7:0] byte mode dci frame input data[7:0] 10930-031
data sheet ad9142 rev. 0 | page 21 of 64 l vds input level requirements there are two types of lvds receivers in the ad9142 . the 16- bit data bus and the frame input share the same lvds receiver design. the dci uses a different lvds design. t he main diffe rence between the two lvds receivers is the required input differential swing level. the data bus and frame receiver require a minimum of 100 mv swing at the input. the dci receiver requires a minimu m of 225 mv s wing at its input. figure 35 shows the lvds input configuration and the required swing levels. because the dci is typically generated from the same bank as the data in the data source, it is recommended that the output swing of the lvds driver be larger th an the required dci input level, thus meeting both input data and dci requir e ments. figure 35 . data interface voltage swing requirements 1.32v +225mv ?225mv 0v 1.1v dcip dci dcin ad9142 dci input lvds level 1.25v +100mv ?100mv 0v 1.15v dnp dn dnn ad9142 data and frame input lvds level dnn dnp dn ad9142 lvds input configuration + ? + ? dcin dcip dci gnd gnd ad9142 to internal digital to internal digital v cm = (v in p + v in n)/2 = 1.2v 100? 100? data receiver dci receiver
ad9142 data sheet rev. 0 | page 22 of 64 interface delay line a four - tap delay line is provided for the user to adjust the ti ming between the data bus and the dci. table 13 specifies the setup and hold times for each delay tap. there is a fixed 1.9 ns delay on the dci when th e delay line is enabled. each tap adds a nominal delay of 300 ps to the fixed delay. t o achieve the best timing margin, that is, to center the setup and hold window in the middle of the data eye, the user may need to add a delay on the data bus with respect to the dci in the data source. figure 36 is an exa mple of calculating the optimal external delay. table 13. setup and hold times d elay setting 0 1 2 3 register 0x5e[7:0] 0x0 0 0x 0 7 0 x 7 f 0 xff register 0 x 5 f[ 2:0 ] 0x0 0 x 0 0 x 0 0x 5 t s (ns) 1 ? 1.25 ? 1.50 ? 1.70 ? 1.93 t h (ns) 2.51 2.82 3. 23 3.64 | t s + t h | (ns) 1.26 1.32 1.53 1.71 1 t he negative sign indicates the direction of the setup time. t he setup time is defined as positive when it is on the left side of the clock edge and negative when it is on the right side of the clock edge. in terface timing requirements th e following example illustrates how to calculate the optimal delay at the data source to achieve the best sampling timing in the delay line - based mode : ? f dci = 200 mhz ? delay s etting = 0 the shadow area in figure 36 is the interface setup and hold time window set to 0. to optimize the interface timing, this window must be placed in the middle of the data transitions. because the input is double data rate, the available data period is 2.5 ns. therefore , t he optimal data bus delay , with respect to the dci at the data source , can be calculated as ns 63 . 0 25 . 1 88 . 1 2 2 |) | | (| = ? = ? + = period data h s delay t t t t spi sequence to enable delay line - based mode it is recommended that the following spi sequence be used to enable the delay line - based mode: 1. 0x79 0x18 /* configure data interface */ 2. 0x5e 0x00 /* delay setting 0 */ 0x5f 0x00 3. 0x5f[3] 1b /* enable the delay line */ figure 36 . example of interfacing timing in the delay line - based mode data ee no data transition input data [150] with optimized dela dci = 200mhz t dela = 0.63ns t data period = 2.5ns t s = 1.25ns t h = 2.51ns 10930-039
data sheet ad9142 rev. 0 | page 23 of 64 fifo operation as is sh own in the data interface section, the ad9142 adopts s ource s ynchronous clocking in the data receiver. the nature of source synchronous clocking is the creation of a separate clock doma in at the receiving device . in the dac, it is the dac clock domain, that is , the dacclk. therefore, there are two clock domains inside of the dac : the dci and the dacclk. o ften , these two clock domains are n ot synchronous , requiring an addi tional stage to adjust the timing for proper data transfer. in the ad9142 , a fifo stage is inserted between the dci and dacclk domai n s to transfer the received data into the core clock domain (dacclk) of the dac. the ad9142 contains a 2 - channel, 16 - bi t wide, 8 - word deep fifo. the fifo acts as a buffer that absorbs timing variati ons between the two clock domains. the timing budget between the two clock domains in the system is signifi cantly relaxed due to the depth of the fifo. figure 37 shows the block diagram of the datapath through the fifo. the input data is latched into the device, formatted, and then written into the fifo register , which is determined b y the fifo write pointer. the value of the write pointer is incremented every time a new word is loaded into the fifo. meanwhile, data is read from the fifo register , which is determined by the read pointer , and fed into the digital datapath. the value of the read pointer is incremented every time data is read into the datapath from the fifo. the fifo pointers are incremented at the data rate , which is the dacclk rate divided by the interpolation rate . valid data is transmitted through the fifo as long as t he fifo does not overflow (full) or underflow ( empty ) . an overflow or underflow condition occurs when the write pointer and read pointer point to the same fifo slot . this simultaneous access of data leads to unreliable data transfer through the fifo and mu st be avoided. normally , data is written to and read from the fifo at the same rate to maintain a constant fifo depth. if data is written to the fifo faster than data is read, the fifo depth increases. if data is read from the fifo faster than data is writ ten to it , the f ifo depth decreases. for optimal timing margin, maintain the fifo depth near half full (a difference of four between the write pointer and read pointer values). the fifo depth represents the fifo pipeline delay and is part of the overall la tency of the ad9142 . figure 37 . block diagram of fifo data receiver i data path q data path i dac dci input data [15:0] frame retimed dci spi fifo reset reg 0x25[0] int dacclk fifo level request reg 0x23 q dac fifo write clock fifo read clock write pointer read pointer fifo slot 0 fifo slot 1 fifo slot 2 fifo slot 3 fifo slot 4 fifo slot 5 fifo slot 6 fifo slot 7 fifo level reset logic fifo data format i[15:0] i[15:0] q[15:0] q[15:0] i/q[31:0] latched data [15:0] 10930-040
ad9142 data sheet rev. 0 | page 24 of 64 resetting the fifo upon power - on of the device , the read and write pointer s start to roll around the fifo from an arbitrary slot ; consequently, the fifo depth is unknown. to avoid a concurrent read and write to the same fifo address and to assure a fixed pipeline delay from power - o n to power - on , it is important to reset the fifo pointers to a known state each time the device p owers on or wakes up. this state is specified in t he requested fifo level (fifo depth and fifo level are used interchangeably in this document), which consists of two parts : the integral fifo level and the fractional fifo level. the integer fifo level rep resents the difference of the states bet ween the read and write point in the unit of input data period (1/ f data ). the fractional fifo level represents the difference of the fifo pointers smaller than the input data period. the resolution of the fractional fifo level is the input data period divided by the interpolation ratio and , thus , it is equal to one dacclk cycle. the exact fifo level, that is , the fifo latency, can be calculated by fifo latency = i ntegral level + fractional level because the fifo ha s eight data slots, there are eight possible fifo integral levels. the max imum supported interpolation rate in the ad9142 is 8 interpolation. therefore, there are eight possible fifo fractional levels. two 3 - bi t registers in register 0x23 are assigned to represent each level separately ; b its [6:4] represent the fifo integral level and b its [2:0] represent the fifo fractional level. for example, if the interpolation rate is 4 and the desired total fifo depth is 4. 5 input data periods, set the fifo_level_config ( register 0x23) to 0x42 (4 here means four data cycles and 2 means two dac cycles, which is half of a data cycle ) . note that there are only four possible fractional levels in the case of 4 interpolation . table 14 shows additional examples of configuring the desired fifo level in various interpolation rate modes. table 14. examples of fifo level configuration inter - polation rate example fifo l evel (1/ f data ) i nteg er level ( register 0x23[6:4]) fractional level ( register 0x23[2:0]) 2 3 + 1/2 3 1 4 4 + 1/4 4 1 8 4 + 3/8 4 3 by defau lt, th e fifo level is 4.0. it can be programmed to any allowed value from 0.0 to 7.x. the max imum allowed number for x is the i nterpolation rate minus 1. for example, in 8 interpolation, the max imum allowed for x is 7 . the following two ways are used to reset the fifo and initialize the fifo level : ? serial p ort (spi) initiated fifo r eset. ? f rame initiated fifo r eset . serial port initiated fifo reset a spi in itiated fifo reset is the most common method to reset the fifo. to initialize the fifo level through the serial port, toggle fifo_spi_reset_request ( register 0x 25[0]) from 0 to 1 and back to 0 . when the write to this register is complete, the fifo level is initialized to the request ed fifo level and the readback of fifo_spi_reset_ack ( register 0x 25[1]) is set to 1 . the fifo level readback, in the same format as the fifo level request, should be within 1 dacclk cycle of the re quested level. for example, if the requested value is 0x4 0 in 4 interpolation, the readback value should be one of the following : 0x33, 0x40, or 0x41. the range of 1 dacclk cycle indicates the default dac latency uncertainty from power - on to power - on w ithout turning on synchronization. the recommended procedure for a serial port fifo r eset is as follows: 1. configure the dac in the desired interpolation mode ( register 0 x 28[ 1:0 ]). 2. ens ure that the dacclk and dci are running and stable at the clock inputs. 3. p rogram register 0x23 to the customized value , if the desired value is not 0x40. 4. request the fifo leve l reset by setting register 0x25[0] to 1. 5. verify that the part acknowledges the request by setting register 0x25[1] to 1. 6. remove the request by setting reg ister 0x25[0] to 0. 7. ve rif y th at th e part drops the acknowledge signal by setting register 0x 25[1] to 0. 8. read back register 0x24 multiple times to verify that the actual fifo level is set to the requested level and that the readback values are stable. by de sign, the readback should be within 1 dacclk around the requested level. f rame initiated fifo reset the frame input has two functions. one function is to indicate the beginning of a byte stream in the byte interface mode , as discussed in the data interface section. the other function is to initialize the fifo level by asserting the frame signal high for at least the time interval required to load complete data to the i and qdacs. this corresponds to one dci period in word mode a nd two dci periods in byte mode. note that this requirement of the frame pulse length is longer than that of the frame signal when it serves only to assemble the byte st r eam. the device accepts either a continuous frame or a one shot frame signal. in the continuous reset mode, the fifo responds to every valid frame pulse and resets itself. in the one shot reset mode, the fifo responds only to the first valid frame pulse after the frame_reset_mode bits (register 0x22[1:0]) are set. therefore, even with a co ntinuous frame input, the fifo reset s one time only ; t his prevents the fifo from toggling between the two states from periodic resets. t he one shot frame reset mode is the default and the recommended mode.
data sheet ad9142 rev. 0 | page 25 of 64 the recommended procedure for a frame i nitiated fi fo r eset is as follows: 1. configure the dac in the desired interpolation mode ( register 0 x 28[ 1:0 ]). 2. en sure that the dacclk and dci are running and stable at the clock inputs. 3. program register 0x23 to the customized value , if the desired value is not 0 x 40. 4. co nfigure the frame_reset_mode bits (register 0x22[1:0]) to 00 b . 5. choose whether continuous or one shot mode is desired by writing 0 or 1 to en_con_frame_reset ( register 0x22[2]). 6. toggle the frame input from 0 to 1 and back to 0 . the pulse width needs to be lo nger than the minimum requirement. a. if the frame input is a continuous clock, turn on the signal. 7. read back frame_reset_ack, register 0x22[3] , to verify that the reset is complete. 8. read back register 0x24 multiple times to verify that the actual fifo level is set to the requested level and the readback values are stable. by design, the readback should be within 1 dacclk around the requested level. monitoring the fifo status the real - time fifo status can be monitored from the spi register 0x24 and reflects the real - time fifo depth after a fifo reset . without timing drifts in the sy stem, this readback should not change from that which resulted from the fifo reset. when there is a timing drift or ot her abnormal clocking situation , the fifo level readback can change. however , as long as the fifo does not overflow or underflow, there is no error in data trans - mission. three status bits in register 0x06, b its [2:0], indicate if there are fifo underflows, overflows, or similar situations. the status of the three bi ts can be latched and used to trigger hardware interrupts, irq 1 and irq2 . to e nable latching and interrupts , configure the corresponding bits in register 0x03 and register 0x04 .
ad9142 data sheet rev. 0 | page 26 of 64 digital datapath figure 38 . block diagram of digital datapath the block diagram in figure 38 shows the functionality of the digital datapath. the digital processing includes ? an i nput power detec tion block ? t hree half - band inte rpolation filters ? a q uadrature modulator consisting of a fine resolution nco and an f s /4 coarse modulation block ? an inverse sinc filter ? a g ain and phase a n d offset adjustment block the interpolation filters accept i and q dat a streams and process them as t wo independent data streams , wh ereas the quadrature modulator and phase adjust ment block accept s i and q data streams as a quadrature data stream. therefore , quadrature input data is required when digital modulation and phase adjustment function s are used. interpolation filter s the transmit path contains three interpolation filters. each of the three interpolation filters provides a 2 increase in output data rate and a low - pass function. the half - band (hb) filters are cas - caded to provide 4 or 8 interpo lation ratios. the ad9142 provides three interpolation modes (see table 6 ) . each mode offers a different usable signal bandwidth in an operating mode. which mode to sel ect depen ds on the required signal bandwidth and the dac update rate. refer to t able 6 for the max imum speed and signal bandwidth of each interpolation mode. the usable bandwidth is defined as the frequency band ov er which the filters have a pass - band ripple of less than 0.001 db and a stop band rejection of greater than 85 db. 2 interpolation mode figure 39 and figure 40 show the pass - band and all - band filter response for 2 mode. note that the transition from the transition band to the stop band is much sharper than the tran - sition from the pass band to the transition band. therefore, when the desired output signal moves out of t he defined pass band, the signal image, which is supposed to be suppressed by the stop band, grows faster than the droop of the signal itself due to the degraded pass - band flatness . i n cases where the degraded image rejection is acceptable or can be compen sated by the analog low - pass filter at the dac output, it is possible to let the output signal extend beyond the specified usable signal bandwidth. figure 39 . pass - band d etail of 2 mode figure 40 . all - band respo nse of 2 mode input power detection and protection hb1 hb2 hb3 inv sinc digital gain and phase and offset adjustment coarse and fine modulation 10930-041 0.02 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 magnitude (db) frequency (hz) 10930-042 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.4 0.2 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 magnitude (db) frequency (hz) 10930-043
data sheet ad9142 rev. 0 | page 27 of 64 4 interpolation mode figure 41 and figure 42 show the pass - band and all - band filter respons e s for 4 mode . figure 41 . pass - band d etail of 4 mode figure 42 . all - band response of 4 mode 8 interpolation mode figure 43 and figure 44 show the pass - band and all - band filter response s for 8 mode . the max imum dac u pdate rate is 1.6 ghz , and the max imum input data rate that is supported in this mode is 200 mhz (1.6 ghz/8). figure 43 . pass - band d etail of 8 mode figure 44 . all - band response of 8 mode table 15 . half - band filter 1 coefficient lower coefficient upper coefficient integer value h( 1 ) h( 55) ? 4 h( 2 ) h( 54) 0 h( 3 ) h( 53) + 13 h( 4 ) h( 52) 0 h( 5 ) h( 51) ? 3 2 h( 6 ) h( 50) 0 h( 7 ) h( 49) +69 h( 8 ) h( 48) 0 h( 9 ) h( 47) ? 134 h( 10 ) h( 46 ) 0 h ( 11) h( 45) +239 h( 12) h( 44) 0 h( 13) h( 43) ? 401 h( 14) h( 42) 0 h( 15) h( 41) +642 h( 16) h( 40) 0 h( 17) h( 39) ? 994 h( 18) h( 38) 0 h( 19) h( 37) +1512 h( 20) h( 36) 0 h( 21) h( 35) ? 2307 h( 22) h( 34) 0 h( 23) h( 33) +3665 h( 24) h( 32) 0 h( 25) h( 31) ? 6638 h(26 ) h( 30) 0 h( 27 ) h( 29 ) +20,754 h( 28) + 32,768 0.02 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 magnitude (db) frequency (hz) 10930-046 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.4 0.2 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 magnitude (db) frequency (hz) 10930-047 0.02 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 magnitude (db) frequency (hz) 10930-048 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.4 0.2 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 magnitude (db) frequency (hz) 10930-049
ad9142 data sheet rev. 0 | page 28 of 64 table 16 . half - band filter 2 coefficient lower coefficient upper coefficient integer value h( 1 ) h( 23) ? 2 h( 2 ) h( 22) 0 h( 3 ) h( 21) + 17 h( 4 ) h( 20) 0 h( 5 ) h( 19) ? 75 h( 6 ) h( 18) 0 h(7 ) h( 17) + 238 h( 8 ) h( 16) 0 h( 9 ) h( 15) ? 660 h( 10 ) h( 14 ) 0 h( 11) h( 13) + 2530 h( 12) + 4096 table 17 . half - band filter 3 coefficient lower coefficient upper coefficient integer value h( 1 ) h(1 1 ) + 29 h( 2 ) h(1 0 ) 0 h( 3 ) h( 9 ) ? 214 h ( 4 ) h( 8 ) 0 h( 5 ) h( 7 ) + 1209 h( 6 ) + 2048 digital modulation the ad9142 provides two modes to modulate the baseband quadrature signal to the desired dac output frequency. ? coarse ( f s /4) m odulation ? fine (nco) m odu lation f s /4 modulation the f s /4 modulation is a convenient and low power modulation mode to translate the input baseband frequency to a fixed f s /4 if frequenc y, f s being the dac sampling rate. when modulation frequencies other than this frequency are requi red, the nco modulation mode must be used. nco modulation th e nco modulation mode makes use of a numerically controlled oscillator (nco) , a phase shifter, and a complex modulator to provide a means for modulating the signal by a programmable carrier signa l. a block diag ram of the digital modulator is shown in figure 45 . the nco modulation allows the dac output signal to be placed anywhere in the output spectrum with very fine frequency resolution. figure 45 . nco modulator block diagram the nco modulator mix es the carrier signal generated by the nco with the i and q signal s . the nco produces a quadrature carrier signal to translate the input signal to a new center fre - quency. a complex car rier signal is a pair of sinusoidal waveforms of the same frequency, offset 90 degrees from each other. the frequency of the complex carrier signal is set via nco _ f req _ tuning _ word [31:0] in register 0x3 1 through register 0x3 4 . the nco operating frequency, f nco , is always equal to f dac , the dacclk frequency . the frequency of the complex carrier signal can be set from dc up to 0.5 f nco . the freque ncy tuning word (ftw) is in two s complement format. it can be calculated as 2 2 dac carrier dac f f f ? ( ) ( ) 0 2 32 = carrier dac carrier f f f ftw ( ) 0 ) ( ) 1 ( < ? = carrier dac carrier f f f ftw 32 2 the generated quadrature carrier signal is mixed with the i and q data. the quadrature products are then summed into the i and q data paths, as shown in figure 45. updating the fr equency tuning word the frequency tuning word registers are not updated immediately upon writing , as are other configuration registers. similar to fifo reset, the nco update can be triggered in two ways. ? spi initiated update ? f rame initiated update cosine sine ~ i data in q data in i data out q data out ftw[31:0] nco phase[15:0] 10930-050
data sheet ad9142 rev. 0 | page 29 of 64 spi i ni tiated u pdate in th e spi initiated update method, the user simply toggles register 0x30[0] (nco_spi_update_req) after configuring the nco settings. the nco is updated on the rising edge ( from 0 to 1 ) in this bit. register 0x30[1] (nco_spi_update_ack) goes high when the nco is updated. a falling edge ( from 1 to 0) in register 0x30[0] clears bit 1 of register 0x30 and prepares the nco for the next update operation. this update method is recommended when there is no requirement to align the dac output from mul tiple devices because spi writes to multiple devices are asynchronous. f rame initiated update when the dac output from multiple devices need s to be well aligned with nco turned on, the frame initiated update is recommended. in this method, the nco s from mu ltiple devices are updated at the same time upon the rising edge of the frame signal. to use this update method, the frame_reset_mode ( register 0x22[1:0]) needs to be set in nco only or fifo and nco, depending on whether fifo reset is needed at the same ti me. the second step is to en sure that the reset mode is in one shot mode ( en_con_frame_reset, register 0x22[2] = 0). when this second step is completed , the nco waits for a valid frame pulse and updates the ftw accordingly. the user can verify if the frame pulse is correctly received by reading register 0x30[6] (nco_frame_ update_ack) wherein a 1 indicates a complete update operation. see the fifo operation section for information to generate a valid frame pulse. d atapath configuratio n configuring the ad9142 datapath starts with the following four parameters: ? t he application requirements of the input data rate ? t he interpolation ratio ? the output signal center frequency ? th e output signal bandwidth given these four parameters, the first step in configuring the datapath is to verify that the device supports the desired input data rate, the dac sampling rate , and the bandwidth requirements . a fter this verification , t he modes o f the interpolation filters can be chosen. if the output signal center frequency is different from the baseband input center frequency, additional frequency offset requirements are determined and applied with on - chip digital modulation. digital quadrature gain and phase adjustment the digital quadrature gain and phase adjustment function enable s compensation of the gain and phase imbalance of the i and q paths caused by analog mismatches between dac i/q outputs, quadrature modulator i/q baseband inputs , and dac/modulator interface i/q paths. the undesired imbalances cause unwanted sideband signal to appear at the quadrature modulator output with significant energy. tuning the quadrature gain and phase adjust values optimize s image rejection in single sideban d radios. quadrature gain adjustment ordinarily, the i and q channels have the same gain or signal magnitude . the quadrature gain adjustment is used to balance the gain between the i and q channels. the digital gain of the i and q channels can be adjusted independently through two 6 - bit registers , idac_gain_adj ( register 0x3f[5:0]) and q dac_gain_adj ( register 0x40[5:0]). t he range of the adjustment is [ 0 , 2] or [ ? , 6 db] with a step size of 2 ? 5 ( ? 30 db). the default setting is 0x20, corresponding to a gain equal to 1 or 0 db. quadrature phase adjustment under normal circumstances, i and q channels have an angle of precisely 90 degrees between them. the quadratur e phase adjust - ment is used to change the angle between the i and q channels. iq_phase_adj[12:0] ( register 0x37 and register 0x38) provide an adjustment range of 14 degrees with a resolution of 0.0035 degrees. i f the original angle is precisely 90 degrees , setting iq_phase_adj[12:0] to 0x0fff adds approximately 14 degrees between i and q dac output s , creating an angle of 104 degrees between the channels . likewise, if the original angle is precisely 90 degrees, setting iq_phase_adj[12:0] to 0x1000 adds appro ximately ? 14 degrees between the i and q dac output s , creating an angle of 76 degrees between the channels . dc offset a djustment the dc value of the i datapath and the q datapath can be controlled independently by adjusting the values in the two 16 - bit regi sters, idac_dc_offset , bits [15:0] and q dac_dc_offset , b its [15:0] ( register 0x3b through register 0 x3e ) . these values are added directly to the datapath values. care should be taken not to overrange the transmitted values. as sh own in figure 46 , the dac offset current varies as a function of the i/qdac_dc_offset values. figure 46 shows the nominal current of the positive node of the dac output, i outp , when t he digital inputs are fixed at midscale (0x0000, twos complement data format) and the dac offset value is swept from 0x0000 to 0xffff . bec ause i outp and i outn are complementary current outputs, the sum of i outp and i outn is always 20 ma. figure 46 . dac output currents vs. dac offset value 0x0000 0x4000 0x8000 0xc000 0xffff 5 10 15 20 5 10 15 20 0 0 dac offset value i outxn (ma) i outxp (ma) 10930-051
ad9142 data sheet rev. 0 | page 30 of 64 inverse sinc filter the ad9142 provides a digital inverse sinc filter to compensate for the dac roll off over frequency. the inverse sinc (sinc ? 1 ) filter is a seven tap fir filter. figure 47 shows the frequency response of sin(x)/x roll off, the inverse sinc filter , and their composite response . the composite response has less than 0.05 db pass - band rippl e up to a frequenc y of 0.4 f dac . to provide the necessary peaking at the upper end of the pas s band, the inverse sinc filter has an intrinsic insertion loss of about 3.8 db. the loss of the digital gain can be offset by increasing the qu adrature gain adj ustment setting on both the i and q data paths to minimize the impact on the output signal - to - noise ratio. how - ever , care is need ed to en sure that the additional digital gain does not cause signal saturation, especially at high output frequencies. the sinc ? 1 filter is disabled by default ; i t can be enabled by setting the invsinc_enable bit to 1 in register 0 x27 [ 7 ] ). figure 47. responses of sin(x)/x roll off (b lue), the sinc ? 1 filter (red) , and the composite of both (black) table 18 . inverse s inc filter lower coefficient upper coefficient integer value h( 1 ) h( 7 ) ? 1 h( 2 ) h( 6 ) + 4 h( 3 ) h( 5 ) ? 16 h( 4 ) + 192 input signal power d etection and p rotection the input signal power detection and protection function d etect s the avera ge power of the dac i nput signal and prevent s over range signals from being pa ssed to the next stage. an over range dac output signal can cause destructive breakdown on power sensitive devices, such as power amplifiers. the power detection an d protection feature of the ad9142 detects over range signals in the dac. when an overrange signal is detected , the protection function either attenuates or mutes the signal to protect the downstream devices from abnormal power surges in the signal. figure 48 shows the block diagram of the power detection and protection f unction . the protection block is at the very last stage of the data path and the detection block u s es a separate path f rom the data path. the design of the detection block guarantees that the worst - case latency of power detecting is shorter than that of the data path. this ensures that the protection circuit initiates before the over range signal reaches the analog dac core . the sum of i 2 and q 2 is calculated as a representation of the input signal power . only the upper six msbs, d[15:10], of data sample s are used in the calculation; consequently, samples whose power is 36 db below the full - scale peak power are not detected. the calculated sample power numbers accumulate through a moving average filter. its output is the average of the input signal power in a certain number of data clo ck cycles. the length of the filter is configurable through the sample_window_length ( regist er 0 x2b[3:0]) . to determine whether the input average power is over range, the device average s the power of the samples in the filter and compares the average power with a user defined threshold, over_threshold_level[11:0] ( register 0 x29 and register 0 x2a) . when the output of the averaging filter is larger than the threshold, the dac output is either attenuated or muted. the appropriate filter length and average power threshold for effective protection are application dependent. it is recommended that exper iments be performed with real - world vectors to determine the values of these parameters. figure 48. block diagram of input signal power detection and protection function 1 ?5 ?4 ?3 ?2 ?1 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.50 0.45 magnitude (db) frequency (hz) 10930-052 averaging filter signal processing engine power protection (attenuate or mute) dac core filter length settings reg 0x2b[3:0] user-defined threshold reg 0x29 and 0x2a[4:0] ave power reg 0x2c and 0x2d[4:0] power detection fifo i 2 + q 2 10930-053
data sheet ad9142 rev. 0 | page 31 of 64 transmit e nable f unction the transmit enable (txen) func tion provides the user a hardware switch of the dac output. the function accepts a cmos signal via pin 6 (txen). when this signal is detec ted high, the transmit path is enabled and the dac transmits the data normally. when this signal is detected low, one of the three act ions related to the dac output is triggered. 1. the dac output is gradually attenuated from full scale gain to 0. the attenuation step size is set in reg ister 0 x 42[ 5:0 ]. 2. the dac is put in sleep mod e and th e output current is turned off. other parts of the dac are still running in this mode. 3. the dac is put in power - down mode. in this mode, not only the dac output current is turned off but the rest of the dac is powered down. this minimizes the power consumption of the dac when the data is not t ransmitting but it takes a bit longer than the first two modes to start to re - transmit data due to the device power - up time. the txen function also provides a gain ramp - up function that lets the user turn on the dac output gradually when the txen signal sw itches from low to high. the ramp - up gain step can be configured using reg ister 0x41[5:0]. although all of these actions can be taken through spi writes, txen provides a much faster way to turn on and off the dac output . the response time of a spi write co mmand is dominated by the spi port communication time . this feature is useful when the user must turn off the dac ver y quickly. digital function con figuration each of the digital gain and phase adjust functions and the i nverse sinc filter can be enabled a nd adjusted independently . the pipeline latencies these blocks add into the data path are different between enabled and disabled . if fixed dac pipeline latency is desired during operation, leave these functions always on or always off after initial configu ration. the digital dc adjust function is always on. the default value is 0; that is, there is no additional dc offset. the pipeline latency that this block adds is a constant , no matter the value of the dc offset. there is also a latency difference betwee n using and not using the input signal power detection and protection function . therefore, to keep the overall latency fixed, leav e this function always on or always off after the initial configuration.
ad9142 data sheet rev. 0 | page 32 of 64 multi d evice synchronizatio n and f ixed l atency a d ac introduces a variation of pipeline latency to a system. the latency variation causes the phase of a dac output to vary from power - on to power - on. therefore, the output from different dac devices may not be perfectly aligned even with well aligned clocks and digital inputs. the skew between multiple dac outputs varies from power - on to power - on. in applications such as transmit diversity or digital pre - distortion, where deterministic latency is desired, the variatio n of the pipeline latency must be minimiz ed. deterministic latency in this document is defined as a fixed time delay from the digital input to the analog output in a dac from power - on to power - on. multiple dac devices are considered synchronized to each other when e ach dac in this group has the s ame constant latency from power - on to power - on. three conditions must be identical in all of the ready - to - sync devices before these devi ces are considered synchronized: ? the phase of dac internal clocks ? the fifo level ? the alignment of the input data very sm all inherent l atency variation the innovative architecture of the ad9142 minimizes the inherent latency variation. the worst - case variation in the ad9142 is two dac c lock cycles. for example, in the case of a 1.5 ghz sample rate, the variation is less than 1.4 ns under any scenario. therefore, without turning on the synchronization engine, the dac outputs from multiple ad9142 devices are guaranteed to be aligned within two dac clock cycles , regardless of the timing between the dci and the dacclk. no additional clocks are required to achieve this accuracy. the user must reset the fifo in each dac devi ce through the spi at star t - up. therefore, the ad9142 can decrease the complexity of system design in multi transmit channel applications. note the alignment of the dci signals in the design . the dci is used as a reference in the ad9142 design to align the fifo and the phase of internal clocks in multiple parts. the achieved dac output alignment depends on how well the dcis are aligned a t the input of each device. the e quation below is the expr ession of the worst - case da c output alignment accuracy in the case of dci mismatches . t sk (out) = t sk ( dci ) + 2/ f dac where: t sk (out) is the worst case skew between the dac output from two ad9142 devices . t sk ( dci) is the skew between two dcis at the dci input of the two ad9142 devices . f dac is the dacclk frequency. the better the alignment of the dcis , the smaller is the overall skew between two dac outputs . further reducing the latency variation for applications that require finer synchronization accuracy (dac latency variation < 2 dac clock cycles), the ad9142 has a provision for enabling multiple devices to be synchroni zed to each other within a single dac clock cycle. t o further reduce the latency variation in the dac, the synchronization machine needs to be turned on and two external clocks (frame and sync) need to be generated in the system and fed to all the dac devi ces. set up and hold timing requirement the sync clock (f sync ) serves as a reference clock in the system to reset the clock generation circuitry in multiple ad9142 devices simultaneously . inside the dac, the sy nc clock is sampled by the dacclk to generate a reference point for aligning the internal clocks , so there is a setup and hold timing requirement between the sync clock and the dac clock. if the user adopt s the continuous frame reset mode, that is, the fi fo and sy nc engine periodically reset, the timing requirements between the sync clock and the dac clock must be met . o therwise , the device can lose lock and corrupt the output . in the one shot frame reset mode, it is still recommended that this timing be m et at the time when the sync routine is run because not meeting the timing can degrade the sync alig nment accuracy by one dac cycle, as shown in table 19. for users who want to synchronize the device in a one - shot manner and conti nue to monitor the synchronization status, the ad9142 provides a sync monitoring mode. it provides a continuous sync and frame clock to synchronize the part once and ignore the clock cycles after the first vali d frame pulse is detected. in this way, the user can monitor the sync status wi thout periodically re synchronizing the device ; t o engage the sync monitoring mode, set register 0 x22[1:0] (frame_reset_ mode) to 11b. table 19. sync cloc k and dac clock setup and hold times falling edge sync timing (default) max unit t s (ns) 246 ps t h (ns) ? 11 ps | t s + t h | (ns) 235 ps
data sheet ad9142 rev. 0 | page 33 of 64 synchronization impl ementation the ad9142 lets the user choose either the rising or falling edge of the dac clock to sample the sync clock, which makes it easier to meet the ti ming requirements. the sync clock , f sync , should be 1/8 f data or slower by a factor of 2n, n being an integer (1, 2, 3 ). note that there is a limit on how slow the sync clock can be because of the ac coupling nature of the sync clock receiver. choose a n appropriate value of the ac coupling capacitors to ensure that the signal swing meets the data sheet specification , as listed in table 2 . the frame clock reset s the fifo in multiple ad9142 devices. the frame can be either a one shot or continuous clock. in either case , the pulse width of the frame must be longer than one dci cycle in the word mode and two dci cycles in the byte mode. when the frame is a continuous clock, f frame should be at 1/8 f data or slower by a factor of 2n, n being an integer (1, 2, 3 ). table 20 lists the requirements of the frame clock in various conditions. table 20. f rame clock speed and pulse w idth requirement sync c lock max imum s peed minimum pulse width one shot n/a 1 for both one shot and continuous sync clocks , w ord mode = one dci cycle and b yte mode = two dci cycles . continuous f data / 8 1 n/a means not applicable. synchronization p rocedure s when the sync accuracy of an application is looser than two dac clock cycles, it is recommended to turn off the synchro - nization machine because there are no additional steps required, other than the regular start - up procedure sequence. for applications that require finer than two - dac clock cycle sync accuracy, it is recommended that the procedure in the synchronization procedure for pll off or synchronization procedure for pll on sections be followed t o set up the system and configur e the device. for more information about the details of the synchronization scheme in the ad9142 and using the synchronization function to correct system skews and drifts, see the dac latency a nd system skews section . synchronization p rocedure for pll off 1. configure the dac interpolation mode and , if nco is used, configure t h e n c o f t w. 2. set up the dac data interface according to the procedu re outlined in the data interface section a nd verify that the dll is locked. 3. choose the appropriate mode in frame_reset_mode. a. if nco is not used, choose fifo only mode. b. if nco is used, it must be synchronized. fifo and nco mod e can then be used. 4. configure b it 2 in register 0 x22 for continuous or one shot reset mode. one shot reset mode is recommended. 5. ensur e that the dacclk, dci, and sync clock to all of the ad9142 devices are runnin g and stable . 6. enable the sync engine by writing 1 to register 0 x 21[ 0 ]. 7. send a valid frame pulse(s) to all of the ad9142 devices. 8. ve rif y that the frame pulse is received by each device by reading back register 0 x 22[3]. all the readback values are 1 . at this point, t he devices should be synchronized. synchronization p rocedure for pll on note that , because the sync clock and pll reference clock share the same clock and the max imum sync clock rate is f data /8, the sa me limit also applies to the reference clock. therefore , only 2 interpolation is supported for synchronization with pll on . 1. set up the pll according to the procedure in the clock multiplication section and e nsure that the pll is l ocked. 2. configure the dac interpolation mode and , if nco is used, configure t h e n c o f t w. 3. set up the dac data interface according to the procedure in the data interface section and verify that the dll is locked. 4. choose the appropri ate mode in frame_reset_mode. a. if nco is not used, choose the fifo only mode. b. if nco is used, it must be synchronized. fifo and nco mode can then be used. 5. configure b it 2 in register 0 x22 for continuous or one shot reset mode. one shot reset mode is recom mended. 6. ensure that dacclk, dci, and sync clock to all of the ad9142 devices are running . 7. enable the sync engine by writing 1 to register 0 x 21[ 0 ]. 8. send a valid frame pulse(s) to all of the ad9142 devices. 9. ve rif y that the frame pulse is received by each device by reading back register 0 x22[3]. all the readback values are 1 . at this point, t he devices should be synchronized.
ad9142 data sheet rev. 0 | page 34 of 64 interrupt request op eration the ad9142 provides an interrupt request output signal on pin 50 and pin 51 ( irq 2 and irq 1 , respectively ) that can be used to notify an external host processor of significant device events. upon assertion of the interrupt, query the device to determine the precise event that occurred. the irq1 pin is an open - drain, active low output. pull the irq1 pin high external to the device. this pin can be tied to th e interrupt pins of other devices with open - drain outputs to wire - or these pins together. te n event flags provid e visibility into the device. these flags are located in the two event flag registers, register 0x0 5 and register 0x0 6 . the behavior of each eve nt flag is independently selected in the interrupt enable registers, register 0x0 3 and register 0x0 4 . when the flag interrupt enable is active, the event flag latches and triggers an external interrupt. when the flag interrupt is disabled, the event flag m onitors the source signal, but the irq 1 and irq 2 pin remain inactive. interrupt w orking m echanism figure 49 shows the interrupt related circuitry and how the event flag signals p ropagate to the irq x output. the interrupt_ enable signal represents one bit from the interrupt enable register. the event_flag_source signal represents one bit from the event flag register. the event _ flag _ source signal represents one of the device signals that can be monitored, such as the pll_ lock signal from the pll phase detector or the fifo _ wa r n i n g _ 1 signal from the fifo controller. when an interrupt enable bit is set high, the corresponding event flag bit reflects a positively trippe d version of the event_flag_ source signal; that is, the event flag bit is latched on the rising edge of the event_flag_source signal . this signal also asserts the external irq pin s. when an interrupt enable bit is set low, the event flag bit reflects the present status of the event_flag_source signal, and the event flag has no effect on the external irq pin s. clear t he latched version of an event flag (the interrupt _ source signal) in one of two ways. the recommended met hod is by writing 1 to the corresponding event flag bit. the second method is to use a hardware or soft ware reset to clear the interrupt _ source signal. the irq 2 circuitry works in the same way as the irq 1 circuitry . any one or multiple event flags can be enabled to trigger the irq 1 and irq 2 pins. the user can select one or both hardware interrupt pins for the enabled event flags. register 0x07 and register 0x08 determine the pin to whic h each event flag is routed. set register 0x07 and register 0x08 to 0 for irq 1 and set these registers to 1 for irq 2 . interrupt service ro utine interrupt request management starts by selecting the set of event flags that require host intervention or monitoring. enable t he events that require host action so that the host is notified when they occur. for events requiring host intervention upon irq x activation, run the following routine to clear an interrup t request: 1. read the status of the event flag bits that are being monitored. 2. set the inte r rupt enable bit low so that the unlatched event _ flag _ source can be monitored directly. 3. perform any actions that may be required to clear the event _ flag _ source . in man y cases, no specific actions may be required. 4. read the event flag to verify th at th e actions taken have cleared the event _ flag _ source . 5. clear the interrupt by writing 1 to the event flag bit. 6. set the inter r upt enable bits of the events to be monitored. note that some event_flag_source signals are latched signals. these signals are cleared by writing to the correspon - ding event flag bit. for more information about each of the event flags , see the device configuration register map a nd description section . figure 49 . simplified schematic of irq circuitry interrupt_enable event_flag_source device_reset event_flag interrupt_ source 1 0 other interrupt sources irq write_1_to_event_flag 10930-054
data sheet ad9142 rev. 0 | page 35 of 64 temperature s ensor the ad9142 has a diode - based temperature sensor for measuring the tempe rature of the die. the temperature reading is accessed using register 0 x 1 d and register 0 x 1 e. the temperature of the die can be calculated as 106 ) 237 , 41 ] 0 : 15 [ ( ? = dietemp t die where t die is the die temperature in degrees celsius. the temperature accur acy is 7 c typi cal over the + 85c to ? 40 c rang e with one point temperature calibration against a known temperature . a typical plot of the die temperature vs. d ie temperature code readback is shown in figure 50. figure 50 . die temperature vs. die temperature code readback estimates of the ambient temperature can be made if the power dissipation of the device is known. for example, if the device power dissipation is 800 mw and the measured die temperature is 50 c, then t he ambient temperature can be calculated as t a = t die C p d ja = 50 C 0.8 20.7 = 33.4 c where: t a is the ambient temperature in degrees celsius. ja is the thermal resistance from junction to ambient of the ad9142 as shown in table 8 . to use the temperature sensor, it must be enabled by setting bit 0 , register 0x1c to 1. in addition, to get accurate readings, the die temperature control register (register 0x1c) should be set to 0x03 . 10930-201 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 temperature (c) die code readback 35000 37000 39000 41000 43000 45000 47000 49000 51000
ad9142 data sheet rev. 0 | page 36 of 64 dac input clock conf igurations the ad 9142 dac sample clock (dacclk) can be sourced directly or by clock multiplying. clock multiplying employs the on - chip phase - locked loop (pll) that accepts a reference clock operating at a submult iple of the desired dacclk rate . the pll then multiplies the reference clock up to the desired dacclk frequency , which can then be used to generate all of the internal clocks required by the dac. the clock multiplier provides a high quality clock that m eets the performance requirements of most applications. using t he on - chip clock multiplier removes the burden of generating and distributing the high speed dacclk. the second mode bypasses the clock multiplier circuitry and let s dacclk be sourced directly to the dac core. this mode le t s the user source a very high qu ality clock directly to the dac core. driving the dacclk a nd refclk inputs the dacclk and refclk differential inputs share similar clock receiver input circuitry. figure 51 shows a simplified circuit diagram of th e input. the on - chip clock receiver has a differential input impedance of about 10 k?. it is self biased to a common - mode voltage of about 1.25 v. the inputs can be driven by differential pecl or lvds drivers with ac coupling between the clock source and the receiver . figure 51 . cl ock receiver input simplified equivalent circuit the minimum input drive lev el to the differential clock input is 1 00 mv p - p differential . the optimal performance is achieved when the clock input signal is between 800 mv p - p differential and 1.6 v p - p diff erential. whether using the on - chip clock multiplier or sourcing the dacclk directly, the input clock signal to the device must have low jitter and fast edge rates to optimize the dac noise performance. direct clocking direct clocking with a low noise cloc k produces the lowest noise spectral density at the dac outputs. to select the differential clk inputs as the source for the dac sampling clock, set the pll enable bit ( register 0 x 12[ 7 ] ) to 0. this powers down the internal pll clock multiplier and selects the input from the dacclkp and dacclkn pins as the source for the internal dac sampl ing clock. the refclk input can remain floating. the device also has clock duty cycle correction circuitry and differ ential input level correction circuitry. enabling these circuits can provide improved performance in some cases. the control bits for these functions ar e in register 0 x10 and register 0 x11 . clock multiplication the on - chip pll clock multiplier circuit generate s the dac sample rate clock from a lower frequency reference clock. when the pll enable bit ( register 0 x12[7]) is set to 1, the clock multiplication circuit generates the dac sampling clock from the lower rate refclk input and t he dacclk input is left floating. the functional diagram of the clock multipli er is shown in figure 52. the clock multiplication circuit operates such that the vco outputs a frequency, f vco , equal to the refclk input signal frequency multiplied by n1 n0. n1 is the divide ratio of the loop divider ; n0 is the divide ratio of the vco divider. f vco = f refclk ( n1 n0) the dac sample clock frequency, f dacclk , is equal to f dacclk = f refclk n1 the output frequency of the vco must be chosen to keep f vco in the optimal operating range of 1.0 gh z to 2.1 ghz. it is important to select a frequency of the reference clock and values of n1 and n0 so that the desired dacclk frequency can be synthesized and the vco output frequency is in the correct range. figure 52 . pll cl ock multiplication circuit 1.25v 5k? 100? 5k? dacclkp/ refp/syncp ad9142 dacclkn/ refn/syncn 1~100nf 1~100nf recommended external circuitry 10930-055 phase frequency detection charge pump pll charge pump current reg 0x14[4:0] divide by 2, 4, 8, or 16 loop divider reg 0x15[1:0] divide by 1, 2, or 4 vco divider reg 0x15[3:2] on-chip loop filter pll loop bw reg 0x14[7:5] vco (1ghz~2.1ghz) adc vco control voltage reg 0x16[3:0] refp/syncp (pin 2) refn/syncn (pin 3) dacclkn (pin 62) dacclkp (pin 61) dacclk pll enable reg 0x12[7] 10930-056
data sheet ad9142 rev. 0 | page 37 of 64 pll settings t he pll circuitry requires three settings to be programmed to their nominal values. the pll values shown in table 21 are the recommended settings for these parameters. tabl e 21 . pll settings pll spi control register register address optimal setting (binary) pll loop bandwidt h 0x14[7:5] 111 pll charge pump current 0x14 [ 4:0 ] 00111 pll cross c ontrol e nable 0x15[4] 0 configuring the vco tuning band t he pll vco has a valid operating range from approximately 1.0 ghz to 2.1 ghz covered in 6 4 overlapping frequency bands. for any desired vco output frequency, there may be several valid pll band select values. the frequency bands of a typical device are sho wn in figure 53 . device - to - device variations and operating temperature affect the actual band frequency range. therefore, it is required that the optimal pll band select value be determined for each individual devi ce. automatic vco band s elect the device has an automatic vco band select feature on chip. using the automatic vco band select feature is a simple and reliable method of configuring the vco frequency band. this feature is enabled by starting the pll in ma nual mode , and then p lacing the pll in auto band select mode by setting register 0 x12 to a v alue of 0xc 0 and then to a value of 0x 8 0. when these values are written, the device executes an automated routine that determines the optimal vco band setting for th e device. the setting selected by the device ensures that the pll remains locked over the full ?40c to +85c operating temperature range of the devi ce without further adjustment. the pll remains locked over the full temperature range even if the temperature during initialization is at o ne of the temperature extremes. figure 53 . pll l ock range for a typical device manual vco band sele ct the device includes a manual band select mo de (pll auto manual enable, register 0 x 12[6] = 1) that lets th e user select the vco tuning band. i n manual mode, the vco band is set directly with the value written to the manual vco band bits ( register 0 x 12 [5:0]). pll enable sequence to enable the pll in automatic or manual mode properly , the following sequence mus t be followed: automatic mode sequence 1. configure the loop divider and the vco d ivider registers for the desired divide ratios. 2. set 00111b to pll charge pump current and 111b to pll l oop bandwidth for the best performance. 3. set the pll m ode to m anual using r egister 0 x12[6] = 1b . 4. enable the pll using register 0 x12[7] = 1b . 5. set the pll m ode to a utomatic using register 0 x12[6] = 0b . 6. enable the pll using register 0 x12[7] = 1b . manual mode 1. configure the loop divider and the vco d ivider registers for the desired di vide ratios. 2. set 00111b to pll charge pump current and 111b to pll l oop bandwidth for the best performance. 3. select the desired band. 4. set the pll m ode to m anual using register 0 x12[6] = 1b . 5. enable the pll using register 0 x12[7] = 1b . 6. enable the pll one more time using register 0 x12[7] = 1b . 61 57 53 49 45 41 37 33 29 25 21 17 13 9 5 1 950 1150 1350 1550 1750 1950 2150 pll band vco frequency (mhz) 10930-057
ad9142 data sheet rev. 0 | page 38 of 64 analog outputs transmit dac operati on figure 54 shows a simplified block diagram of the transmit path dacs. the dac core consists of a current source array, a switch core, digi tal control logic, and full - scale output current control. the dac full - scale output current (i outfs ) is nominally 20 ma. the output currents from the iout1p/iout2p and iout1n/ iout2n pins are complementary, meaning that the sum of the two currents always e quals the full - scale current of the dac. the digital input code to the dac determines the effective differential current delivered to the load. figure 54 . simplified block diagram of dac core the dac has a 1.2 v band gap referen ce with an output imped - ance of 5 k . the reference output voltage appears on the refio pin. when using the internal reference, decouple the refio pin to avss with a 0.1 f capacitor. use the internal reference only for external circuits that draw dc curre nts of 2 a or less. for dynami c loads or static loads greater than 2 a, buffer the refio pin. if desired, the internal reference can be overdriven by applying an external reference (from 1.10 v to 1.30 v) to the refio pin. a 10 k external resistor, r set , must be connected from the fsadj pin to avss. this resistor, together with the reference control amplifier, sets up the correct internal bias currents for the dac. because the full - scale current is inversely proportional to this resistor, the tolerance o f r set is reflected in the full - scale output amplitude. the full - scale current equation, wh ere the dac gain is set i ndivid ually for the q and i dacs in register 0x40 and register 0x44 , respectively, is as follows: ? ? ? ? ? ? ? ? ? ? ? ? + = 16 3 72 for nominal values of v ref (1.2 v), r set (10 k ), and dac gain (512), the full - scale current of the dac is typically 20.16 ma. the dac full - scale current can be adjusted from 8.64 ma to 31.68 ma by setting the dac g ain parameter, as shown in figure 55. figure 55 . dac full - scale current vs. dac gain code transmit dac transfer function the output currents from the iout1p/iout2p and iout1n/ iout2n pins are complementary, meaning that the sum of the two current s always equals the full - scale current of the dac. the digital input code to the dac determines the effective differen - tial current delivered to the l oad. iout1p/iout2p provide maxi mum output current when all bits are high. the output currents vs. daccode for the dac outputs is expressed as outfs n outp i daccode i ? ? ? ? ? ? = 2 (1) i outn = i outfs C i outp (2) where daccode = 0 to 2 n ? 1 . transmit dac output configurations the optimum noise and distortion performance of the ad9142 is realized when it is configured for differential operation. t he common - mode rejection of a transformer or differential amplifier significantly reduces t he common - m ode error sources of the dac outputs . these common - mode error sources include even - order distortion products and noise. the enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude increases. this is due to the first - order cancellation of various dynami c common - mode distortion mechanisms, digital feed - through, and noise. i dac iout1p iout1n q dac iout2n iout2p current scaling i dac fs adjust reg 0x18, 0x19 q dac fs adjust reg 0x1a, 0x1b 0.1f 10k? r set fsadj refio 5k? 1.2v 10930-058 35 0 0 1000 dac gain code i fs (ma) 30 25 20 15 10 5 200 400 600 800 10930-059
data sheet ad9142 rev. 0 | page 39 of 64 figure 56 shows the most basic dac output circuitry. a pair of resistors, r o , convert each of the complementary output currents to a differe ntial voltage output, v out . because the current outputs of the dac are high impedance, the differential driving point impedance of the dac outputs, r out , is equal to 2 r o . see figure 57 for the output voltage wav eforms. figure 56 . basic transmit dac output circuit figure 57 . output voltage waveforms the common - mode signal voltage, v cm , is calculated as o fs cm r i v = 2 the peak output voltage, v peak , is calculated as v peak = i fs r o in this circuit configuration, the single - ended peak voltage is the same as the peak differential output voltage. interfacing to modul ators the ad9142 interfaces to the adl537x fa mily of modulators with a minimal number of components. an example of the recommended interface circuitry is shown in figure 58. figure 58 . typical interface circuitry between the ad9142 and t he adl537x family of modulators the baseband inputs of the adl537x family require a dc bias of 500 mv. the nominal midscale output current on each output of the dac is 10 ma ( one - half the full - scale curren t). therefore, a single 50 ? resistor to ground from each of the dac outputs results in the desired 500 mv dc common - mode bias for the inputs to the adl537x. t he addition of the load resistor in parallel with the modulator inputs reduces t he signal level . the peak - to - peak voltage swing of the transmitted signal is ) 2 ( ) 2 ( l b l b fs signal r r r r i v + = baseband filter implementation most applications require a baseband anti - imaging filter between the dac and the modulator to filter out nyquist images and broadband dac noi se. the filter can be inserted between the i - v resistors at the dac output and the signal level setting resistor across the modulator input. this configuration establishes the input and output impedances for the filter. figure 59 shows a fifth - order, low - pass filter. a common - mode choke is placed between the i - v resistors and the remainder of the filter to remove the common - mode signal produced by the dac and to prevent the common - mode signal from being converted t o a differential signal, which can appear as unwanted spurious signals in the output spectrum. splitting the first filter capacitor into two and grounding the center point creates a common - mode low - pass filter, which provid es additional common - mode rejecti on of high frequency signals. a purely differential filter can pass common - mode signals. for more details about interfacing the ad9142 dac to an iq modulator, refer to the c ircuits from the lab cn - 0205 , interfacin g the adl5375 i/q modulator to the ad9122 dual c hannel, 1.2 gsps high speed dac on the analog devices website. figure 59 . dac modulator interface with fifth - order, low - pass filte r r o r o v ip + v in ? v outi iout1p iout1n r o r o v qp + v qn ? v outq iout2p iout2n 10930-060 +v peak v cm 0 ?v peak v n v p v out 10930-061 rbip 50? rbin 50? 67 66 ibbn ibbp ad9142 adl537x rbqn 50? rbqp 50? 59 58 rli 100? rlq 100? iout1n iout1p iout2p iout2n qbbp qbbn 10930-062 ad9142 50? 50? 33nh 33nh 3.6pf 33nh 33nh 140? 6pf 3pf 3pf 22pf 22pf adl537x 10930-063
ad9142 data sheet rev. 0 | page 40 of 64 reducing lo leakage and unwanted sidebands analog quadrature modulators can introduce unwanted signals at the local oscillator ( lo ) frequency due to dc offset voltages in the i and q baseband inputs, as well as feedthrough pat hs from the lo input to the out put. the lo feedthrough can be nulled by applying the correct dc offset voltages at the dac output using the digital dc o ffset adjustments (register 0x3b through register 0x3e ). effective sideband suppression requires both gain and phase matching of th e i and q signals. the i/q phase adjust registers (register 0x3 7 and register 0x38 ) and the dac fs adjust registers (register 0x18 through register 0x1b ) can be used to calibrate the i and q transmit paths to optimize sideband suppression. for more inform ation about suppressing lo leakage and sideband image, refer to application note an - 1039, correcting imperfections in iq modulators to improve rf signal fidelity and a pplication note an - 1100 , wireless transmitter iq balance and sideband suppression from the analog devices w ebsite.
data sheet ad9142 rev. 0 | page 41 of 64 example start - up routine to ensure reliable start - up of the ad9142 , certain sequences must be fo llowed . this section shows an example start - up routine . device configuration and start - up sequence ? f data = 200 mhz, interpolation is 8 . ? input data is baseband data . ? f out = 350 mhz . ? pll is enabled, f ref = 200 mhz . ? fine nco is enabled, inverse sinc f ilter is enabled . ? a d elay line - based mode is used with an interface delay setting of 0 . derived pll settings the following pll settings can be derived from the device configuration: ? f dac = 200 8 = 1600 mhz . ? f vco = f dac = 1600 mhz (1 ghz < f vco < 2 ghz) . ? vco d ivider = f vco / f dac = 1 . ? loop d ivid er = f dac / f ref = 8 . derived nco settings the following nco settings can be derived from the device configuration: ? f dac = 200 8 = 1 600 mhz . ? f carrier = f out = 35 0 mhz . ? ftw = f carrier / f dac 2 32 = 0x 38000000 . start - u p sequence 1. power up the device (no specific power supply sequence is required) . 2. apply stable dac clock. 3. apply stable dci clock. 4. feed stable input data. 5. issue h/w reset (optional) . /* device configuration register write sequence. must be written in sequence for every device after reset*/ 0x00 0x20 /* issue software reset */ 0 x 20 0 x 01 /* device startup configuration */ 0 x 79 0 x 18 /* device startup configuration */ 0 x 80 0 xad /* device startup configuration */ 0 xe 1 0 x 1 a /* device startup configuration */ /* configure pll */ 0x14 0x e 3 /* configure pll loop bw and charge pump current */ 0 x 15 0 xc 2 /* configure vco divider and loop divider */ 0x12 0xc0 /*e nable the pll */ 0 x 12 0 x 80 /* configure data interface */ 0x5e 0x00 /* delay setting 0 */ 0x5f 0x08 /* enable the delay l ine */ /* configure interpolation filter */ 0x28 0x03 /* 8 interpolation */ /* reset fifo */ 0 x 25 0 x 01 read 0 x 25 [ 1 ] /* expect 1 b if the fifo reset is complete */ read 0x24 /* t he readback should be one of the three values: 0x37, 0x40 , or 0 x 41 */ /* configure nco */ 0x27 0x40 /* e nable nco */ 0 x 31 0 x 00 0 x 32 0 x 00 0 x 33 0 x 00 0 x 34 0 x 38 0 x 30 0 x 01 read 0x30[1] /* expect 1b if the nco u pdate is complete */ /* enable inverse sinc filter */ 0 x 27 0 xc 0 /* power up dac outputs */ 0x01 0x00
ad9142 data sheet rev. 0 | page 42 of 64 device configuration register map a nd description table 22 . device configuration register map reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 common [7:0] reserved spi_lsb_first device_reset reserved 0x00 rw 0x01 pd_control [7:0] pd_idac pd_qdac pd_datarcv reserved pd_device pd_dacclk pd_frame 0xc0 rw 0x03 interrupt_ enable0 [7:0] reserved enable_ sync_ lost enable_ sync_locked enable_ sync_done enable_pll_ lost enable_pll_ locked enable_over_ threshold e nable_ dacout_ muted 0x00 rw 0x04 interrupt_ enable1 [7:0] reserved enable_fifo_ underflow enable_fifo_ overflow enable_fifo_ warning 0x00 rw 0x05 interrupt_ flag0 [7:0] reserved sync_lost sync_locked sync_done pll_lost pll_locked over_ threshold dacout_ muted 0x00 r 0x06 interrupt_ flag1 [7:0] reserved fifo_ underflow fifo_over - flow fifo_ warning 0x00 r 0x07 irq_sel0 [7:0] reserved sel_sync_ lost sel_sync_ locked sel_sync_ done sel_pll_lost sel_pll_ locked sel_over_ threshold sel_dacout _muted 0x00 rw 0x08 irq_sel1 [7:0] reserved sel_fifo_ underflow sel_fifo_ overflow sel_fifo_ warning 0x00 rw 0x10 dacclk_ receiver_ ctrl [7:0] dacclk_ dutycycle_ correction reserved dacclk_ crosspoint_ ctrl_enable dacclk_crosspoint_level 0xf f rw 0x11 refclk_ receiver_ ctrl [7:0] dutycycle_ correction reserved refclk_ crosspoint_ ctrl_enable refclk_crosspoint_level 0x b f rw 0x12 pll_ctrl0 [7:0] pll_enable auto_ manual_sel pll_manual_band 0x00 rw 0x14 pll_ctrl2 [7:0] pll_loop_bw pll_cp_current 0xe7 rw 0x15 pll_ctrl3 [7: 0] diglogic_divider reserved crosspoint_ ctrl_en vco_divider loop_divider 0xc9 rw 0x16 pll_status0 [7:0] pll_lock reserved vco_ctrl_voltage_readback 0x00 r 0x17 pll_status1 [7:0] reserved pll_band_readback 0x00 r 0x18 idac_fs_adj0 [7:0] idac_fullscale_a djust_lsb 0xf9 rw 0x19 idac_fs_adj1 [7:0] reserved idac_fullscale_adjust_ msb 0xe1 rw 0x1a qdac_fs_adj0 [7:0] qdac_fullscale_adjust_lsb 0xf9 rw 0x1b qdac_fs_adj1 [7:0] reserved qdac_fullscale_adjust_ msb 0x01 rw 0x1c die_temp_ sensor_ctrl [7:0] reserve d fs_current ref_current die_temp_ sensor_en 0x02 rw 0x1d die_temp_lsb [7:0] die_temp_lsb 0x00 r 0x1e die_temp_msb [7:0] die_temp_msb 0x00 r 0x1f chip_id [7:0] chip_id 0x0a r 0x20 interrupt _ config [7:0] interrupt _ configuration 0x00 rw 0x21 sync_ctrl [7:0] reserved sync_clk_ edge_sel sync_ enable 0x00 rw 0x22 frame_rst_ ctrl [7:0] reserved frame_ reset_ack en_con_ frame_reset frame_reset_mode 0x12 rw 0x23 fifo_level_ config [7:0] reserved integral_fifo_level_request reserved fractional_fifo_level_req uest 0x40 rw 0x24 fifo_level_ readback [7:0] reserved integral_fifo_level_readback reserved fractional_fifo_level_readback 0x00 r 0x25 fifo_ctrl [7:0] reserved fifo_spi_ reset_ack fifo_spi_ reset_ request 0x00 rw 0x26 data_ format_sel [7:0] data_ format data_pairin g data_bus_ invert reserved data_bus_ width 0x00 rw 0x27 datapath_ ctrl [7:0] invsinc_ enable nco_enable iq_gain_adj_ dcoffset_ enable iq_phase_ adj_enable reserved fs4_ modulation_ enable nco_side - band_sel send_idata_ to_qdac 0x00 rw
data sheet ad9142 rev. 0 | page 43 of 64 0x28 int erpolation _ ctrl [7:0] reserved interpolation_mode 0x00 rw 0x29 over_ threshold_ ctrl0 [7:0] threshold_level_request_lsb 0x00 rw 0x2a over_ threshold_ ctrl1 [7:0] reserved threshold_level_request_msb 0x00 rw 0x2b over_ threshold_ ctrl2 [7:0] enable_ prot ection iq_data_ swap reserved sample_window_length 0x00 rw 0x2c input_power_ readback_lsb [7:0] input_power_readback_lsb 0x00 r 0x2d input_power_ readback_msb [7:0] reserved input_power_readback_msb 0x00 r 0x30 nco_ctrl [7:0] reserved nco_frame_ update_ac k spi_nco_ phase_rst_ ack spi_nco_ phase_ rst_req reserved nco_spi_ update_ack nco_spi_ update_req 0x00 rw 0x31 nco_freq_ tuning_ word0 [7:0] nco_ftw0 0x00 rw 0x32 nco_freq_ tuning_ word1 [7:0] nco_ftw1 0x00 rw 0x33 nco_freq_ tuning_ word2 [7:0] nco_ftw 2 0x00 rw 0x34 nco_freq_ tuning_ word3 [7:0] nco_ftw3 0x10 rw 0x35 nco_phase_ offset0 [7:0] nco_phase_offset_lsb 0x00 rw 0x36 nco_phase_ offset1 [7:0] nco_phase_offset_msb 0x00 rw 0x37 iq_phase_ adj0 [7:0] iq_phase_adj_lsb 0x00 rw 0x38 iq_phase_ adj1 [7:0] reserved iq_phase_adj_msb 0x00 0 rw 0x3b idac_dc_ offset0 [7:0] idac_dc_offset_lsb 0x00 rw 0x3c idac_dc_ offset1 [7:0] idac_dc_offset_msb 0x00 rw 0x3d qdac_dc_ offset0 [7:0] qdac_dc_offset_lsb 0x00 rw 0x3e qdac_dc_ offset1 [7:0] qdac_dc_offset_msb 0x00 rw 0x3f idac_gain_adj [7:0] reserved idac_gain_adj 0x20 rw 0x40 qdac_gain_ adj [7:0] reserved qdac_gain_adj 0x20 rw 0x41 gain _ step _ ctrl0 [7:0] reserved ramp_up_step 0x01 rw 0x42 gain _ step _ ctrl1 [7:0] dac_output_ status dac_output_ on ramp_down_st ep 0x01 rw 0x43 tx_enable_ ctrl [7:0] reserved txenable_ gainstep_en txenable_ sleep_en txenable_ power_ down _en 0x07 rw 0x44 dac_output_ ctrl [7:0] dac_output_ ctrl_en reserved fifo_warning_ shutdown_en over - threshold _ shutdown_ en reserved fifo_error_ sh utdown_ en 0x8f rw 0x5e data_rx_ctrl0 [7:0] dly_tap_lsb 0xff rw 0x5f data_rx_ctrl1 [7:0] reserved dlyline_en dly_tap_msb 0x07 rw 0x79 device _ config0 [7:0] device _ configuration0 0x00 rw 0x7f version [7:0] version 0x05 r 0x80 device _ config1 [7:0] device _ configuration1 0x00 r w 0xe1 device _ config2 [7:0] device _ configuration2 0x00 rw
ad9142 data sheet rev. 0 | page 44 of 64 spi configure regist er address: 0x00, reset: 0x00, name: c ommon table 23 . bit descriptions for c ommon bits bit name settings description reset access 6 spi_lsb_first serial port communication, msb - first or lsb - first selection. 0 x 0 rw 0 msb f irst . 1 lsb f irst . 5 device_reset the device reset s when 1 is written to this bit. device_reset is a self clear bit. after the reset , the bit returns t o 0 automatically. the readback is always 0 . 0 x 0 rw power - down control registe r address: 0x01, reset: 0xc0, name: pd_control table 24 . bit descriptions for pd_control bits bit name settings description reset access 7 pd_idac the i dac is powered down when pd_idac is set to 1. this bit powers down only the analog portion of the idac. the idac digital data path is not affected. 0 x 1 rw 6 pd_qdac the qdac is powered down when pd_qdac is set to 1. this bit powers down only the analog p ortion of the qdac. the qdac digital data path is not affected. 0 x 1 rw 5 pd_datarcv the data interface circuitry is powered down when pd_datarcv is set to 1. this bit powers down the data interface and the w rite side of the fifo. 0 x 0 rw 2 pd_device th e bandgap circuitry is powered down when set to 1 . this bit powers down the entire chip. 0 x 0 rw 1 pd_dacclk the dac clocking power s down when pd_device is set to 1. this bit power s down the dac clocking path and , thus , the majority of the digital functio ns. 0 x 0 rw 0 pd_frame the frame receiver power s down when pd_frame is set to 1. the frame signal is internally pulled low. set to 1 when frame is not used. 0 x 0 rw interrupt enable0 re gister address: 0x03, reset: 0x00, name: interrupt_enable0 table 25 . bit descriptions for interrupt_enable0 bits bit name settings description reset access 6 enable_sync_lost enable i nterrupt for sync lost . 0 x 0 rw 5 enable_sync_locked enable i nterrupt for sync lock . 0 x 0 rw 4 enable_sync_done enab le i nterrupt for sync done. 0 x 0 rw 3 enable_pll_lost enable i nterrupt for pll lost . 0 x 0 rw 2 enable_pll_locked enable i nterrupt for pll locked . 0 x 0 rw 1 enable_over_threshold enable i nterrupt for overthreshold . 0 x 0 rw 0 enable_dacout_muted enable i nterrupt for dacout muted . 0 x 0 rw interrupt enable1 re gister address: 0x04, reset: 0x00, name: interrupt_enable1 table 26 . bit descriptions for interrupt_enable1 bits bit name settings description reset access 2 enable_fifo_underfl ow enable i nterrupt for fifo underflow. 0 x 0 rw 1 enable_fifo_overflow enable i nterrupt for fifo overflow. 0 x 0 rw 0 enable_fifo_warning enable i nterrupt for fifo warning . 0 x 0 rw
data sheet ad9142 rev. 0 | page 45 of 64 interrupt flag0 regi ster address: 0x05, reset: 0x00, name: interrupt_fla g0 table 27 . bit descriptions for interrupt_flag0 bits bit name settings description reset access 6 sync_lost sync_lost is set to 1 when sync is lost. 0 x 0 r 5 sync_locked sync_locked is set to 1 when sync is locked. 0 x 0 r 4 sync_ done sync_done is set to 1 when sync is done. 0 x 0 r 3 pll_lost pll_lo st is set to 1 when pll los es lock. 0 x 0 r 2 pll_locked pll_locked is set to 1 when pll is locked. 0 x 0 r 1 over_threshold over_threshold is set to 1 when input power is over threshol d. 0 x 0 r 0 dacout_muted dacout_muted is set to 1 when the dac output is muted (mid scale dc ). 0 x 0 r interrupt flag1 regi ster address: 0x06, reset: 0x00, name: interrupt_flag1 table 28 . bit descriptions for interrupt_flag1 bits bit name settings description reset access 2 fifo_underflow fifo_underflow is set to 1 when the fifo read pointer catches the fifo write pointer. 0 x 0 r 1 fifo_overflow fifo_overflow is set to 1 when the fifo write pointer catches the fifo read pointer. 0x0 r 0 fifo_warning fifo_warning is set to 1 when the fifo is one slot from empty ( 1) or full ( 6 ). 0 x 0 r interrupt select0 re gister address: 0x07, reset: 0x00, name: irq_sel0 table 29 . bit descriptions for irq_sel0 bits bit name settings description reset access 6 sel_sync_lost 0 selects the irq1 pin . 0 x 0 rw 1 selects the irq2 pin . 5 sel_sync_locked 0 selects the irq1 pin . 0 x 0 rw 1 selects the irq2 pin . 4 sel_sync_done 0 selects the irq1 pin . 0 x 0 rw 1 selects the irq2 pin . 3 sel_pll_lost 0 selects the irq1 pin . 0 x 0 rw 1 selects the irq2 pin . 2 sel_pll_locked 0 selects the irq1 pin . 0 x 0 rw 1 sel ects the irq2 pin . 1 sel_over_threshold 0 selects the irq1 pin . 0 x 0 rw 1 selects the irq2 pin . 0 sel_dacout_muted 0 selects the irq1 pin . 0 x 0 rw 1 selects the irq2 pin .
ad9142 data sheet rev. 0 | page 46 of 64 interrupt select1 re gister address: 0x08, reset: 0x00, name: irq_sel1 table 30 . bit descriptions for irq_sel1 bits bit name settings description reset access 2 sel_fifo_underflow 0 selects the irq1 pin . 0 x 0 rw 1 selects the irq2 pin . 1 sel_fifo_overflow 0 selects the irq1 pin . 0 x 0 rw 1 selects the irq2 pin . 0 sel_fifo_warning 0 selects the irq1 pin . 0 x 0 rw 1 sele cts the irq2 pin . dac clock receiver c ontrol register address: 0x1 0, reset: 0x f f, n ame: dacclk_receiver_ctrl table 31 . bit descriptions for dacclk_receiver_ctrl bits bit name settings description reset access 7 dacclk_dutycycle_correction enable s duty cycle correction at the dacclk input. for best performance, t he default and recommended status is turned on. 0 x 1 rw 5 dacclk_crosspoint_ctrl_enable enables cross point control at the dacclk input. for best perform ance, t he default and recommended status is turned on . 0 x 1 rw [ 4:0 ] dacclk_crosspoint_level a twos complement value. for best performance, i t is recommended to set dacclk_crosspoint_level to the default value. 0 x 1 f rw 0111 1 hi ghest crosspoint. 1 111 1 l owest crosspoint. ref clock receiver c ontrol register address: 0x11, r eset: 0x b f, na me: refclk_receiver_ctrl table 32 . bit descriptions for refclk_receiver_ctrl bits bit name settings description reset access 7 dutycycle_co rrection enable s duty cycle correction at the refclk input. for best performance, t he default and recommended status is turned off . 0 x 0 rw 5 refclk_crosspoint_ctrl_enable enable s cross point control at the refclk input. for best performance, t he default and recommended status is turned off . 0 x 0 rw [ 4:0 ] refclk_crosspoint_level a twos complement value. for best performance, i t is recommended to set refclk_crosspoint_level to the default value. 0 x 1 f rw 0111 1 h ighest crosspoint . 1111 1 l owest crossp oint.
data sheet ad9142 rev. 0 | page 47 of 64 pll control register address: 0x12, reset: 0x00, name: pll_ctrl0 table 33 . bit descriptions for pll_ctrl0 bits bit name settings description reset access 7 pll_enable enable s pll clock multiplier. 0 x 0 rw 6 auto_manual_sel pll band selection mode. 0 x 0 rw 0 automatic m ode . 1 manual m ode . [ 5:0 ] pll_manual_band pll band setting in manual mode. 64 bands in total , covering a 1 g hz to 2.1 g hz vco range. 0 x 00 rw 000000 l owest band (1 ghz). 111111 h ighest ban d ( 2.1 ghz). pll control register address: 0x14, reset: 0xe7, name: pll_ctrl2 table 34 . bit descriptions for pll_ctrl2 bits bit name settings description reset access [ 7:5 ] pll_loop_bw select s the pll loop filter bandwidth. the default and recommended setting is 111 for optimal pll performance. 0 x 7 rw 0x00 l owest setting. 0x1f h ighest setting. [ 4:0 ] pll_cp_current sets nominal pll charge pump current. the default and recommended setting is 00111 for optimal pll perf ormance . 0 x 07 rw 0x00 l owest setting. 0x1f h ighest setting. pll control register address: 0x15, reset: 0xc9, name: pll_ctrl3 table 35 . bit descriptions for pll_ctrl3 bits bit name settings description reset access [ 7:6 ] d iglogic_divider refclk to pll digital clock divide ratio. the pll digital clock drives the interna l pll logics. the divide ratio must be set to en sure that the pll digital clock is below 75 mhz. 0 x 3 rw 00 f refclk / f dig = 2 . 01 f refclk /f dig = 4 . 10 f refclk /f dig = 8 . 11 f refclk /f dig = 16 . 4 crosspoint_ctrl_en enable loop divider crosspoint control. the default and recommended setting is turned o ff (0) for optimal pll performance. 0 x 0 rw [ 3:2 ] vco_divider pll vco divider. this divider d etermines the ratio of the vco frequency to the dacclk frequency. 0 x 2 rw 00 f vco /f dacclk = 1 . 01 f vco /f dacclk = 2 . 10 f vco /f dacclk = 4 . 11 f v co /f dacclk = 4 . [ 1:0 ] loop_divider pll loop divider. this divider determines the ratio of th e dacclk frequency to the refclk frequency. 0 x 1 rw 00 f dacclk /f refclk = 2 . 01 f dacclk /f refclk = 4 . 10 f dacclk /f refclk = 8 . 11 f dacclk /f refclk = 16 .
ad9142 data sheet rev. 0 | page 48 of 64 pll status register address: 0x16, reset: 0x00, name: pll_status0 table 36 . bit descriptions for pll_status0 bits bit name settings description reset access 7 pll_lock pll clock multiplier output is stable. 0 x 0 r [ 3:0 ] vco_ctrl_voltage_readback vco control voltage readback. a binary value. 0 x 0 r 1111 t he highest vco control voltage. 0111 t he mid value when a proper vco band is selected. when the pll is locked, selecting a higher vco band decreases this value and selecting a lower vco band increases this value. 0000 t he lowest vco control voltage. pl l status register address: 0x17, reset: 0x00, name: pll_status1 table 37 . bit descriptions for pll_status1 bits bit name settings description reset access [ 5:0 ] pll_band_readback indicates the vco band currently selected. 0 x 00 r i dac fs adjust lsb re gister address: 0x18, reset: 0xf9, name: idac_fs_adj0 table 38 . bit descriptions for idac_fs_adj0 bits bit name settings description reset access [ 7:0 ] idac_fullscale_adjust_lsb see register 0x19. 0 xf 9 rw i dac fs adjust msb regist er address: 0x19, reset: 0xe1, name: idac_fs_adj1 table 39 . bit descriptions for idac_fs_adj1 bits bit name settings description reset access [ 1:0 ] idac_fullscale_adjust_msb i dac f ull -s cale a djust , bits [9:0] set s the full - scale current of the i dac. the full - scale current can be adjusted from 8.64 ma to 31.68 ma. the default value (0x1f9) sets the full - scale current to 20 ma. 0 x 1 rw qdac fs adjust lsb r egister address: 0x1a, reset: 0xf9, name: qdac_fs_adj0 table 40 . bit descriptions for qdac_fs_adj0 bits bit name settings description reset access [ 7:0 ] qdac_fullscale_adjust_lsb see register 0x1b. 0 xf 9 rw
data sheet ad9142 rev. 0 | page 49 of 64 qdac fs adjust msb r egister address: 0x1b, reset: 0x01, name: qdac_fs_adj1 table 41 . bit descriptions for qdac_fs_adj1 bits bit name settings description reset access [ 1:0 ] qdac_fullscale_adjust_msb q dac f ull - s cale a djust , bits [9:0] sets the full - scale current of the q dac. the full - scale current can be adjusted fr om 8.64 ma to 31.68 ma. the default value (0x1f9) sets the full - scale current to 20 ma. 0 x 1 rw die temp erature sensor control regis ter address: 0x1c, reset: 0x02, name: die_temp_sensor_ctrl table 42 . bit descriptions for die_temp_se nsor_ctrl bits bit name settings description reset access [ 6:4 ] fs_current temperature sensor adc full - scale current. using the default setting is recommended. 0 x 0 rw 000 50 a. 001 62.5 a. 110 125 a. 111 137.5 a. [ 3:1 ] ref_current temperature sensor adc reference current. using the default setting is recommended. 0 x 1 rw 000 12.5 a. 001 19 a. 110 50 a. 111 56.5 a. 0 die_temp_sensor_en enable the on - chip temperature sensor. 0 x 0 rw die temp erature lsb register address: 0x1d, reset: 0x00, name: die_temp_lsb table 43 . bit descriptions for die_temp_lsb bits bit name settings description reset access [ 7:0 ] die_temp_lsb see register 0x1e. 0 x 00 r die temp erature msb register address: 0x1e, reset: 0x00, name: die_temp_msb table 44 . bit descriptions for die_temp_msb bits bit name settings description reset access [ 7:0 ] di e_temp_msb die t emp erature, bits[15:0] indicate the approximate die temperature . for more information, see the temperature s ensor section. 0 x 00 r chip id register address: 0x1f, reset: 0x0a, name: chip_id table 45 . bit descriptions for chip_id bits bit name settings description reset access [ 7:0 ] chip_id the ad9142 chip id is 0x0a . 0 x 0 a r
ad9142 data sheet rev. 0 | page 50 of 64 interrupt c onfiguation register address: 0x20, reset: 0x 00, name: interrupt _ config table 46 . bit descriptions for interrupt_config bits bit name settings description reset access [ 7:0 ] interrupt _ c onfig uration 0 x 00 test m ode . 0 x 00 rw 0 x 01 recommended mode (described in interrupt request operation section) . s ync ctrl register address: 0x21, reset: 0x00, name: sync_ctrl table 47 . bit descriptions for sync_ctrl bits bit name settings description reset access 1 sync_clk_edge_sel select s t he sampling edge of the dacclk on the sync clk . 0 x 0 rw 0 sync clk is sampled by rising edges of dacclk . 1 sync clk is sampled by falling edges of dacclk . 0 sync_enable enable s multichip synchronization . 0 x 0 rw f rame reset ctrl register addres s: 0x22, reset: 0x12, name: frame_rst_ctrl table 48 . bit descriptions for frame_rst_ctrl bits bit name settings description reset access 3 frame_reset_ack frame reset acknowledge. this bit is set to 1 when a valid frame pulse is rec eived. 0 x 0 r 2 en_con_frame_reset reset mode selection. 0 x 0 rw 0 r esponds to only the first valid frame pulse and resets the fifo and/or nco on e time only. this is the default and recommended mode. 1 responds to every valid frame pulse and resets the fifo and/or nco accordingly . [ 1:0 ] frame_reset_mode the s e bits determ ine what is to be reset when the device receives a valid frame signal. 0 x 2 rw 00 fifo only . 01 nco only . 10 fifo and nco . 11 none .
data sheet ad9142 rev. 0 | page 51 of 64 fifo level configura tion register address: 0x23, reset: 0x40, name: fifo_level_c onfig table 49 . bit descriptions for fifo_level_c onfig bits bit name settings description reset access [ 6:4 ] integral_fifo_level_request sets the integral fifo level. this is th e difference between the read pointer and the write pointer values in the unit of input data rate (f data ). the default and recommended fifo level is integral level = 4 and fractional level = 0. see the fifo operatio n section for details. 0 x 4 rw 000 0 . 001 1 . 111 7 . [ 2:0 ] fractional_fifo_level_request sets the fractional fifo level. this is the difference between the read pointer and the write pointer values in the unit of dacclk rate (f dac ). the maximum allowed setting value = interpolation rate ? 1. see the fifo operation section for details. 0 x 0 rw 000 0 . 001 1 . max allowed setting. 001 in 2 . 003 in 4 . 007 in 8 . fifo leve l readback register address: 0x24, reset: 0x00, name: fifo_level_readback table 50 . bit descriptions for fifo_level_readback bits bit name settings description reset access [ 6:4 ] integral_fifo_level_readback the integral fifo level read back. the difference between the overall fifo level request and readback should be within two dacclk cycles. see the fifo operation section for details. 0 x 0 r [ 2:0 ] fractional_fifo_level_readback the fra c tio nal fifo level read back. this value should be used in combinati on with the readback i n b it[ 6:4 ]. 0 x 0 r fifo ctrl register address: 0x25, reset: 0x00, name: fifo_ctrl table 51 . bit descriptions for fifo_ctrl bits bit name settings d escription reset access 1 fifo_spi_reset_ack acknowledge a serial port initialized fifo reset. 0 x 0 r 0 fifo_spi_reset_request initialize a fifo reset via the serial port. 0 x 0 rw
ad9142 data sheet rev. 0 | page 52 of 64 data format select r egister address: 0x26, reset: 0x00, name: data_forma t_sel table 52 . bit descriptions for data_format_sel bits bit name settings description reset access 7 data_format select b inary or twos complement data format. 0 x 0 rw 0 input data in twos complement format . 1 input data in b inary format . 6 data_pairing indicate i/q data pairing on data input. 0 x 0 rw 0 i samples are paired with the next q samples . 1 i samples are paired with the prior q samples . 5 data_bus_invert swap the bit order of the data input port. msbs become the lsbs: d[15:0] changes to d[0:15]. 0 x 0 rw 0 the o rder of the data bits corresponds to the pin descriptions in table 9 . 1 the order of the data bits is inverted . 0 data_bus_width data interface mode. see the lvds input data ports section for information about the operation of the different interface modes. 0 x 0 rw 0 w ord mode; 16- bit interface bus width. 1 b yte mode; 8 - bit interface bus width. datapath contr ol register address: 0x27, reset: 0x00, name: datapath_ctrl table 53 . bit descriptions for datapath_ctrl bits bit name settings description reset access 7 invsinc_enable enable the i nverse sinc f ilter. 0 x 0 rw 6 nco_enable enable t he nco. 0 x 0 rw 5 iq_gain_adj_dcoffset_enable enable digital iq gain adjust ment and dc offset. 0 x 0 rw 4 iq_phase_adj_enable enable digital iq phase adjustment. 0 x 0 rw 2 fs 4 _modulation_enable enable f s / 4 modulation function. 0 x 0 rw 1 nco_sideband_sel s elect s the single - side nco modulation image. 0 x 0 rw 0 the nco outputs the high - side image. 1 the nco outputs the low - side image. 0 send_idata_to_qdac send the idata to the qdac. when enabled, i data is sen t to both the i dac and the qdac . the q data path still runs , and the q data is ignored. 0 x 0 rw interpolation contro l register address: 0x28, reset: 0x00, name: interpolation_ctrl table 54 . bit descriptions for interpolation_ctrl bits bit name settings description rese t access [ 1:0 ] interpolation_mode interpolation rate and mode selection. 0 x 0 rw 00 2 m ode 1; u se hb1 f ilter . 10 4 m ode; u se hb1 and hb2 f ilters . 11 8 m ode; u se all three filters (hb1, hb2 , and hb3) .
data sheet ad9142 rev. 0 | page 53 of 64 over t hreshold ctrl0 regis ter addre ss: 0x29, reset: 0x00, name: over_threshold_ctrl0 table 55 . bit descriptions for over_threshold_ctrl0 bits bit name settings description reset access [ 7:0 ] threshold_level_request_lsb see register 0x2a. 0 x 0 rw over t hreshold ctrl 1 register address: 0x2a, reset: 0x00, name: over_threshold_ctrl1 table 56 . bit descriptions for over_threshold_ctrl1 bits bit name settings description reset access [ 4:0 ] threshold_level_request_msb minimum average input power (i 2 + q 2 ) to trigger the input power protection function. 0 x 00 rw over threshold ctrl2 register address: 0x2b, reset: 0x00, name: over_threshold_ctrl2 table 57 . bit descriptions for over_threshold_ctrl2 bits bit name settings descriptio n reset access 7 enable_protection enable input power protection. 0 x 0 rw 6 iq_data_swap swap i and q data in average power calculation. 0 x 0 rw [ 3:0 ] sample_window_length number of data input samples for power averaging. 0 x 0 rw 0000 512 iq data sam ple pairs. 0001 1024 iq data sample pairs. 1010 2 19 iq data sample pairs. 1011 to 1111 invalid. input power readback lsb register address: 0x2c, reset: 0x00, name: input_power_readback_lsb table 58 . bit des criptions for input_power_readback_lsb bits bit name settings description reset access [ 7:0 ] i nput_power_readback_lsb see register 0x2d. 0 x 0 r input power readback msb register address: 0x2d, reset: 0x00, name: input_power_readback_msb table 59 . bit descriptions for input_power_readback_msb bits bit name settings description reset access [ 4:0 ] input_power_readback_msb input signal averag e power readback . 0 x 00 r
ad9142 data sheet rev. 0 | page 54 of 64 nco control register address: 0x30, reset: 0x00, name: nco_ctrl ta ble 60 . bit descriptions for nco_ctrl bits bit name settings description reset access 6 nco_frame_update_ack frequency tuning word update request from frame . 0 x 0 r 5 spi_nco_phase_rst_ack nco phase spi reset acknowledge . 0 x 0 r 4 spi_nco_phase_rst_req nco phase spi reset request . 0 x 0 rw 1 nco_spi_update_ack frequency tuning word update acknowledge . 0 x 0 r 0 nco_spi_update_req frequency tuning word update reques t from spi. 0 x 0 rw nco_freq_tuning_word 0 register address: 0x31, r eset: 0x00, name: nco_freq_tuning_word0 table 61 . bit descriptions for nco_freq_tuning_word0 bits bit name settings description reset access [ 7:0 ] nco_ftw 0 see register 0x34. 0 x 00 rw nco_freq_tuning_word 1 register address: 0x32, reset: 0x00, name: nco_freq_tuning_word1 table 62 . bit descriptions for nco_freq_tuning_word1 bits bit name settings description reset access [ 7:0 ] nco_ftw 1 see register 0x34. 0 x 00 rw nco_freq_tuning_word 2 register address: 0x33, reset: 0x00, name: nco_freq_tuning_word2 table 63 . bit descriptions for nco_freq_tuning_word2 bits bit name settings description reset access [ 7:0 ] nco_ftw 2 see register 0x34. 0 x 00 rw nco_freq_tuning_word 3 register address: 0x34 , reset: 0x10, name: nco_freq_tuning_word3 table 64 . bit descriptions for nco_freq_tuning_word3 bits bit name settings description reset access [ 7:0 ] nco_ftw 3 ftw[31:0] is the 32 - bit frequency tuning word that determines the frequen cy of the complex carrier generated by the on - chip nco. the frequency is not updated when the ftw registers are written. the values are only updated when a serial port update or frame update is initialized in r egister 0x30. it is in twos complement format. 0 x 10 rw nco_phase_offset0 re gister address: 0x35, reset: 0x00, name: nco_phase_offset0 table 65 . bit descriptions for nco_phase_offset0 bits bit name settings description reset access [ 7:0 ] nco_phase_offset_lsb see register 0x36. 0 x 00 rw
data sheet ad9142 rev. 0 | page 55 of 64 nco_phase_offset1 re gister address: 0x36, reset: 0x00, name: nco_phase_offset1 table 66 . bit descriptions for nco_phase_offset1 bits bit name settings description reset access [ 7:0 ] nco_phase_offset_msb this register set s the initial phase of the complex carrier signal upon reset. the phase offset spans from 0 degrees to 360 degrees . each bit represent s an offset of 0.0055 degrees . this value is in twos complement format. 0 x 00 rw iq_phase_adj0 regist er address: 0x37, re set: 0x00, name: iq_phase_adj0 table 67 . bit descriptions for iq_phase_adj0 bits bit name settings description reset access [ 7:0 ] iq_phase_adj_lsb see register 0x38. 0 x 00 rw iq_phase_adj1 regist er address: 0x38, reset: 0x000, nam e: iq_phase_adj1 table 68 . bit descriptions for iq_phase_adj1 bits bit name settings description reset access [ 4:0 ] iq_phase_adj_msb iq p hase a d j ust, bits [12:0] , is used to insert a phase offset between the i and q datapaths. it pro vides an adjustment range of 14 degrees with a step of 0.0035 deg rees . this value is in twos compl e ment . see the quadrature phase adjustment section for more information. 0 x 0 rw idac_dc_offset0 regi ster address: 0x3b, reset: 0x00, name: idac_dc_offset0 table 69 . bit descriptions for idac_dc_offset0 bits bit name settings description reset access [ 7:0 ] idac_dc_offset_lsb see register 0x3c. 0 x 00 rw idac_dc_offset1 regi ster address: 0x3c, reset: 0x00, name: idac_dc_offset1 table 70 . bit descriptions for idac_dc_offset1 bits bit name settings description reset access [ 7:0 ] idac_dc_offset_msb idac dc o ffset , bits [15:0] , is a dc val ue that is added direct ly to the sample va lues written to the i dac. 0 x 00 rw qdac_dc_offset0 regi ster address: 0x3d, reset: 0x00, name: qdac_dc_offset0 table 71 . bit descriptions for qdac_dc_offset0 bits bit name settings description reset access [ 7:0 ] qd ac_dc_offset_lsb see register 0x3e. 0 x 00 rw
ad9142 data sheet rev. 0 | page 56 of 64 qdac_dc_offset1 regi ster address: 0x3e, reset: 0x00, name: qdac_dc_offset1 table 72 . bit descriptions for qdac_dc_offset1 bits bit name settings description reset access [ 7:0 ] qdac_dc_ offset_msb qdac dc o ffset , bits [15:0] , is a dc value that is added directly to the sample values written to the qdac. 0 x 00 rw idac_gain_adj regist er address: 0x3f, reset: 0x20, name: idac_gain_adj table 73 . bit descriptions for id ac_gain_adj bits bit name settings description reset access [ 5:0 ] idac_gain_adj this register is the 6 - bit digital gain adjust on the i channel. the bit weighting is msb = 2 0 , lsb = 2 ? 5 , which yields a multiplier range of 0 to 2 or ? to 6 db. the defaul t gain setting is 0x20, which maps to unity gain (0 db). 0 x 20 rw qdac_gain_adj regist er address: 0x40, reset: 0x20, name: qdac_gain_adj table 74 . bit descriptions for qdac_gain_adj bits bit name settings description reset access [5 : 0 ] qdac_gain_adj this register is the 6 - bit digital gain adjust on the q channel. the bit weighting is msb = 2 0 , lsb = 2 ? 5 , which yields a multiplier range of 0 to 2 or ? to 6 db. the default gain setting is 0x20, which maps to unity gain (0 db). 0 x 20 rw gain step control0 r egister address: 0x41, reset: 0x01, name: gain _ step _ ctrl0 table 75 . bit desc riptions for gain _ step _ ctrl0 bits bit name settings description reset access [ 5:0 ] ramp_up_step this register sets the step size of the increasing gain. the digital gain increases by the configured amount in every four dac cycles until the g ain reaches t he setting in i/qdac_gain_adj ( register 0 x3f and register 0x40 ). the bit weighting is msb = 2 1 , lsb = 2 ? 4 . note that t he value in this register should not be greater than the values in the i/q dac_gain_adj ( register 0 x3f and register 0x40). 0 x 01 rw gain step control1 r egister address: 0x42, reset: 0x01, name: gain _ step _ ctrl1 table 76. bit descriptions for gain _ step _ ctrl1 bits bit name settings description reset access 7 dac_output_status this bit indicates the dac output on/off status. when the dac output is automatically turned off, this bit is 1 . 0 x 0 rw 6 dac_output_on in the cas e where the dac output is automatically turned off in the input power protection mode or t x enable mode, this register allows for turning on the dac output manually. it is a self clear bit. 0 x 0 r [ 5:0 ] ramp_down_step this register sets the step size of t he decreasing gain. the digital gain decreases by the configured amount in every four dac cycle s until the gain reaches zer o. the bit weighting is msb = 2 1 , lsb = 2 ? 4 . note that the value in this register should not be greater than the values in the i/q dac _gain_adj ( register 0 x3f and register 0x40). 0 x 01 rw
data sheet ad9142 rev. 0 | page 57 of 64 t x enable control regis ter address: 0x43, reset: 0x07, name: tx_enable_ctrl table 77 . bit descriptions for tx_enable_ctrl bits bit name settings description reset access 2 txenabl e_gainstep_en dac output gradually turns on/off under the control of the t x ena bl e signa l from the txen pin according to the settings in register 0 x41 and regis ter 0x42 . 0 x 1 rw 1 txenable_sleep_en when set to 1, the device is put in sleep mode when the t xenable si gnal from the txen pin is low. 0 x 1 rw 0 txenable_power_down_en when set to 1, the device is put in power down mode when txenable signal from the txen pin is low. 0 x 1 rw dac output control r egister address: 0x44, reset: 0x8f, name: dac_output_ ctrl table 78 . bit descriptions for dac_output_ctrl bits bit name settings description reset access 7 dac_output_ctrl_en enable the dac output control. this bit needs to be set to 1 to enable the rest of the bits in this register. 0 x 1 rw 3 fifo_warning_shutdown_en when this bit and bit 7 are both high, if a fifo warning occurs , the dac output shut s down automatically. by default , this function is on. 0 x 1 rw 2 overthreshold_shutdown_en the dac output is turned off when the input a verage power is greater than the predefined threshold. 0 x 1 rw 0 fifo_error_shutdown_en the dac output is turned off when the fifo reports warnings. 0 x 1 rw data receiver test c ontrol register address: 0x5e, reset: 0xff, name: data_rx_ctrl0 table 79 . bit descriptions for data_rx_ctrl0 bits bit name settings description reset access [ 7:0 ] dly_tap_lsb see register 0x5f[2:0]. 0 xff rw data receiver test c ontrol register address: 0x5f, reset: 0x07, name: data_rx_ctrl1 table 80 . bit descriptions for data_rx_ctrl1 bits bit name settings description reset access 3 dlyline_en 1 = enable the data interface. 0 x 0 rw [ 2:0 ] dly_tap_msb four available de lay settings. see the int erface delay line section for more information. 0 x 7 rw 00 0 x 000 01 0 x 007 10 0x0 7 f 11 0x 5 ff
ad9142 data sheet rev. 0 | page 58 of 64 device configuration 0 register address: 0x79, reset: 0x00, name: device _ config 0 table 81 . bit descriptions for device _ co nfig 0 bits bit name settings description reset access [ 7:0 ] device _ configuration 0 0 x 18 recommended setting for device start - up configuration 0 x 00 rw v ersion register address: 0x7f, reset: 0x05, name: version table 82 . bit descript ions for version bits bit name settings description reset access [ 7:0 ] v ersion chip v ersion 0 x 05 r device configuration 1 register address: 0x80, reset: 0x00, name: device _ config 1 table 83 . bit descriptions for device _ config 1 bits bit name settings description reset access [ 7:0 ] device _ configuration 1 0 xad recommended setting for device start - up configuration 0 x 00 rw device configuration 2 register address: 0xe1, reset: 0x00, name: device _ config 2 table 84 . bi t descriptions for device _ config 2 bits bit name settings description reset access [ 7:0 ] device _ configuration2 0 x 1 a recommended setting for device start - up configuration 0 x 00 rw
data sheet ad9142 rev. 0 | page 59 of 64 dac latency a nd system skews figure 60 . breakdo wn of pipeline latencies dac latency variatio ns dacs, like any ot her devices with internal multi phase clocks, have an inherent pipeline latency variation. figure 60 shows the b reakdown of pipeline latencies in the ad9142 . the highlighted section , including the fifo and the clock generation circuitry, is where the pipeline latencies vary . upon each power - on, the status of both the fifo and the clock generation state machine is arbitrar y. this leads to varying latency in these two blocks. fifo latency variation there are eight data slots in the fifo. the fifo read and write pointers circulate the fifo from slot 0 to slot 7 and back to slot 0. the fifo depth is defined as the number of fif o slots that are required for the read point er to catch the write pointer. it is also the time a particu lar piece of data stay s in the fifo from the point that it is written into the fifo to the point where it is read out f rom the fifo. therefore, the late ncy of the fifo is equivalent to its depth. figure 61 is an example of fifo latency variation. the latency in c ase 2 is two data cycles longer than that in c ase 1. if other latencies are the same, the skew between the dac outputs in these two cases is, likewise, two data cycles. therefore , to keep a constant fifo latency, the fifo depth needs to be reset to a pre - defined value. theoretically, an y value other than 0 is valid but typically it is set to 4 to maximiz e the capacity of absorbing the rate fluctuation between the read and write side. figure 61 . example of fif o latency difference figure 62 shows two equivalent cases of fifo latency of four data cycles . although neither the read n or the write pointer match each other in these two cases , the fifo depth is the same in both cases. also , note that the beginning slots of the data stream in the two cases are not the same , but the read and write pointers point to the same piece of data in both cases. this does not affect the alignment accuracy of the dac outputs as long as the data and the dcis are well aligned at multiple devices . figure 62 . example of e qual fifo l atencies fifo dacclk i and q dac hb1 fixed latency hb2 hb3 other digital functionalities dacclk/2 dacclk/4 dacclk/8 dci fifo wrptr fifo rdptr varying latency varying latency fixed latency div 2 div 2 div 2 data interface 10930-064 data 2 data 3 data 4 data 5 fifo case 1: latency = 4 dci cycles fifo wrptr fifo rdptr data 6 data 7 data 1 data 0 data 2 data 3 data 4 data 5 fifo case 2: latency = 6 dci cycles fifo wrptr fifo rdptr data 6 data 7 data 1 data 0 10930-065 data 2 data 3 data 4 data 5 fifo latency = 4 dci cycles fifo wrptr fifo rdptr data 6 data 7 data 1 data 0 data 7 data 0 data 1 data 2 fifo fifo wrptr fifo rdptr data 3 data 4 data 6 data 5 10930-066
ad9142 data sheet rev. 0 | page 60 of 64 clock generation latency v ariation the state machine of the clock generation circuitry is an other source of latency variations ; t his type of latency variation results from inherent phase uncertainty of the static frequency divider s . the divided down clock can be high or low at the rising edge of the input clock , unless specifically forced to a known state. this means that whenever there is interpolation (when slower clocks need to be internally generated by dividing down the dacclk), there is an inherent latency variation in the dac . figure 63 is an example of this latency variation in 2 interpolation. there are two phase possibilities in the dacclk/2 clock. the dacclk/2 clock is used to read data from the fifo and to drive the interpo - lation filter. regard less of which clock edge is used to drive the digital circuit, there is a latency of one dac clock cycle between c ase 1 and c ase 2 (see figure 62) . bec ause the power - on state arbitrarily falls in one of the two cas es , the phase uncertainty of the divider appears as a varying skew between two dac outputs. figure 63 . latency variation in 2 interpolation from clock generation correcting s ystem s kews generally , it is assumed that the input data and the dci among multiple devices are well aligned to each other . depending on the system design, the data and dci being input into each dac can originate from various fpgas or asics. without synchronizing the data sources, the output of one data sou rce can be skewed from that of another . the alignment between multiple data sources can also drift over temperature. figure 64 shows an example of a 2 - channel transmitter with two data sources and two dual dacs. a constan t but un known phase offset appear s between the outputs of the dac devices , even if the dac does not introduce any latency variati ons. the multi device synchronization in the ad9142 can be u s ed to compensate the skew due to misalignment of the data sources by resetting the two sides of the fifo independently through two external reference clock s : the frame and the sync clock. the offset between the two data sources is then absorbed by the fifo and clock generation block in the dac. for more information about using the multi device synchronization function, refer to the synchronization implementation section. figure 64 . dac output skew from skewed input data and dci hb1 hb2 hb3 dacclk dacclk/2 (case 1) dacclk/2 (case 2) latency variation = 1 dacclk cycle 10930-067 dac dac dac dac 16-bit data frame dci 16-bit data frame dci 16-bit data frame dci dci 16-bit data frame sync clock 4 2 match sync line for all data gen data skew data gen data gen master ref clock 10930-068
data sheet ad9142 rev. 0 | page 61 of 64 pack aging and o rdering i nformation outline dimensions figure 65 . 72 - lead lead frame chip scale package [lfcsp_vq] 10 mm 10 mm body, very thin quad (cp - 72 - 7) dimensions shown in millimeters ordering guide model 1 temperature range p ackage description package option ad9142 bcpz ? 40 c to + 85 c 72 - lead lfcsp_vq cp -72 -7 ad9142 bcpzrl ? 40 c to + 85 c 72 - lead lfcsp_vq cp -72 -7 ad9142 -m 5372 - ebz evaluation board connected to adl5372 modulator ad9142 - m5375 - ebz evaluation board connected to adl5375 modulator 1 z = rohs compliant part. compliant to jedec standards mo-220-vnnd-4 0.20 ref 0.80 max 0.65 ty p 1.00 0.85 0.80 0.05 max 0.02 nom 1 18 54 37 19 36 72 55 0.50 0.40 0.30 8.50 ref pin 1 indic a t or sea ting plane 12 max 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 0.50 bsc pin 1 indic a t or coplanarit y 0.08 06-25-2012- a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. t o p view exposed p ad bot t om view 10.10 10.00 sq 9.90 9.85 9.75 sq 9.65 0.25 min 6.15 6.00 sq 5.85
ad9142 data sheet rev. 0 | page 62 of 64 notes
data sheet ad9142 rev. 0 | page 63 of 64 notes
ad9142 data sheet rev. 0 | page 64 of 64 notes ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10930 - 0 - 11/12(0)
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